DDC316_17 Datasheet, PDF (19/28 Pages) Texas Instruments – 16-Channel, Current-Input Analog-to-Digital Converter

DDC316
www.ti.com......................................................................................................................................................... SBAS370A – MARCH 2008 – REVISED APRIL 2009
VOLTAGE REFERENCE
The reference voltage is used to reset the integration
capacitors before an integration cycle begins. It is
also used by the ADCs when they measure the
voltage stored on the integrators after an integration
cycle ends. During this sampling, the external
reference must supply the charge needed by the
ADCs. For an integration time of 20µs, this charge
translates to an average VREF current of
approximately 270µA. The amount of charge needed
by the ADC is independent of the integration time;
therefore, increasing the integration time lowers the
average current. For example, an integration time of
40µs lowers the average VREF current to 135µA.
It is critical that VREF be stable during the different
modes of operation (see Figure 7). The ADC
measures the voltage on the integrator with respect
to VREF. Since the integrator capacitors are initially
reset to VREF, any drop in VREF, from the time the
capacitors are reset to the time when the converter
measures the integrator output, introduces an offset.
It is also important that VREF be stable over longer
periods of time because changes in VREF
correspond directly to changes in the full-scale range.
Finally, VREF should introduce as little additional
noise as possible. For these reasons, it is strongly
recommended that the external reference source be
buffered with an operational amplifier.
The DDC316 offers two options for driving the
reference voltage: through an external buffer or
through an internal buffer. In both the cases, the
reference voltage is generated external to the chip
using an accurate reference, such as the REF3140.
Internal VREF Buffer
The DDC316 provides an internal VREF buffer to
drive the four on-chip ADCs. The reference voltage
must be provided at VREF_IN (pin 4B), as shown in
Figure 14. The external capacitors at the VREF pins
are necessary to stabilize the internal buffer. It is
recommended that these capacitors be placed as
close as possible to the device under test. Also, good
quality capacitors with low ESR (< 1Ω) are necessary
for optimum performance. High ESR capacitors will
lead to oscillation of the internal buffer. Ceramic
capacitors with ESR < 1Ω at 100kHz are
recommended.
+5V
0.47mF
1
+
10mF
REF3140 ^{2 10kW}
+
3
10mF
VREF (4A, 6A, 6B)
0.1mF
DDC316
VREF_IN (4B)
0.1mF
Figure 14. Recommended Circuit when Using the
Internal VREF Buffer
External VREF Buffer
The internal buffer can be turned off using the control
bits as explained in the Configuring the Modes
section under Bit 4 and Table 10. For this option,
configure the driving circuit as illustrated in Figure 15.
The voltage reference is generated by a +4.096V
reference. A low-pass filter to reduce noise connects
the reference to an operational amplifier configured
as a buffer. The VREF_IN pin must be left
disconnected.
This amplifier used as buffer should have low noise
and input/output common-mode ranges that support
VREF. Even though the circuit in Figure 15 might
appear to be unstable as a result of the large output
capacitors, it works well for most operational
amplifiers. It is not recommended that series
resistance be placed in the output lead to improve
stability because it can cause a drop in VREF and
produce large offsets.
+5V
0.47mF
1
10kW
REF3140 ²
+
3
10mF
+5V
0.1mF
7
2
OPA350
3
0.1mF ₄
6
+
10mF
VREF (4A, 6A, 6B)
0.1mF
DDC316
VREF_IN (4B)
Figure 15. Recommended Circuit when Using an External VREF Buffer
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