CDC2510_15 Datasheet, PDF (7/13 Pages) Texas Instruments – 3.3V Phase-Lock Loop Clock Driver

CDC2510
3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER
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SCAS597B − DECEMBER 1997 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
PHASE ERROR
vs
CLOCK FREQUENCY
0
−0.1
VDD = 3.3 V
TA = 25°C
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
25 35 45 55 65 75 85 95 105 115 125
fclk − Clock Frequency − MHz
Figure 3
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
9
VDD = 3.3 V
8 _{TA = 25°C}
7
6
5
4
3
2
1
0
25 35 45 55 65 75 85 95 105 115 125
fclk − Clock Frequency − MHz
Figure 5
OUTPUT DUTY CYCLE
vs
CLOCK FREQUENCY
57%
55%
VDD = 3.3 V
CL = 30 pF
53%
51%
49%
47%
45%
43%
30 40 50 60 70 80 90 100 110 120 130
fclk − Clock Frequency − MHz
Figure 4
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
VCC = 3.6 V
TA = 25°C
CLY = CLF = 30 pF
200
150
100
50
0
20
40
60
80
100 120 140
fclk − Clock Frequency − MHz
Figure 6
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