CDC2510_15 Datasheet, PDF (5/13 Pages) Texas Instruments – 3.3V Phase-Lock Loop Clock Driver

CDC2510
3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER
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SCAS597B − DECEMBER 1997 − REVISED DECEMBER 2004
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
fclock Clock frequency
25 125 MHz
Input clock duty cycle
40% 60%
Stabilization time†
1 ms
† _{Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a}
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C_L = 30 pF (see Note 5 and Figures 1 and 2)^‡
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.165 V
MIN TYP MAX
VCC = 3.3 V
± 0.3 V
MIN
TYP MAX
tphase _error,
reference
(see Figure 3)
66 MHz < CLKIN↑ < 100 MHz
FBIN↑
−0.7...0.1
ns
tphase _error
− jitter
(see Note 6)
tsk(o)§
Jitter(pk-pk)
Duty cycle
reference
(see Figure 4)
CLKIN↑ = 100 MHz
Any Y or FBOUT
F(clkin > 66 MHz)
FBIN↑
−500
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
−50
−100
43%
− 310
ps
200 ps
100 ps
55%
tr
Any Y or FBOUT
1.3 1.9 0.8
2.1 ns
tf
Any Y or FBOUT
1.7 2.3 1.2
2.5 ns
‡ _{These parameters are not production tested.}
§ _{The tsk(o) specification is only valid for equal loading of all outputs.}
NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is − 600 ps to 50 ps for the 5% VCC range.
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