CDC2510_15 Datasheet, PDF (6/13 Pages) Texas Instruments – 3.3V Phase-Lock Loop Clock Driver

CDC2510
3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER
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SCAS597B − DECEMBER 1997 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
500 W
Input
tpd
50% VCC
Output
2V
0.4 V
tr
2V
50% VCC
tf
3V
0V
VOH
0.4 V
VOL
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
tphase _error
FBOUT
Any Y
tsk(o)
Any Y
Any Y
tsk(o)
Figure 2. Phase Error and Skew Calculations
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