CDC2510_15 Datasheet, PDF (1/13 Pages) Texas Instruments – 3.3V Phase-Lock Loop Clock Driver

D Use CDCVF2510A as a Replacement for
this Device
D Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D Distributes One Clock Input to One Bank of
Ten Outputs
D Single Output Enable Terminal Controls All
Ten Outputs
D External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
D On-Chip Series Damping Resistors
D No External RC Network Required
D Operates at 3.3-V V_CC
D Packaged in Plastic 24-Pin Thin Shrink
Small-Outline Package
CDC2510
3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER
ą
SCAS597B − DECEMBER 1997 − REVISED DECEMBER 2004
PW PACKAGE
(TOP VIEW)
AGND 1
V_CC 2
1Y0 3
1Y1 4
1Y2 5
GND 6
GND 7
1Y3 8
1Y4 9
V_CC 10
G 11
FBOUT 12
24 CLK
23 AV_CC
22 V_CC
21 1Y9
20 1Y8
19 GND
18 GND
17 1Y7
16 1Y6
15 1Y5
14 V_CC
13 FBIN
description
The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It
is specifically designed for use with synchronous DRAMs. The CDC2510 operates at 3.3-V V_CC and provides
integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV_CC to ground.
The CDC2510 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
G
CLK
1Y
(0:9)
FBOUT
X
L
L
L
L
H
L
H
H
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2004, Texas Instruments Incorporated
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