BQ24707 Datasheet, PDF (7/36 Pages) Texas Instruments – 1-4 Cell Li+ Battery SMBus Charge Controller With Independent Comparator and Advanced Circuit Protection

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SLUSA78B – JULY 2010 – REVISED MARCH 2011
ELECTRICAL CHARACTERISTICS (continued)
4.5 V ≤ V_(VCC) ≤ 24 V, 0°C ≤ T_J ≤ 125°C, typical values are at T_A = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
SMBus TIMING CHARACTERISTICS
t_R
t_F
t_W(H)
t_W(L)
t_SU(STA)
t_H(STA)
SCLK/SDATA rise time
SCLK/SDATA fall time
SCLK pulse width high
SCLK pulse width low
Setup time for START condition
START condition hold time after which first clock
pulse is generated
1
300
4
50
4.7
4.7
4
t_SU(DAT)
Data setup time
t_H(DAT)
Data hold time
t_SU(STOP)
Setup time for STOP condition
t_(BUF)
Bus free time between START and STOP condition
F_S(CL)
Clock frequency
HOST COMMUNICATION FAILURE
250
300
4
4.7
10
100
t_timeout
t_BOOT
t_WDI
SMBus bus release timeout⁽³⁾
Deglitch for watchdog reset signal
Watchdog timeout period, ChargeOption()
bit [14:13] = 01⁽⁴⁾
25
35
10
35
44
53
t_WDI
Watchdog timeout period, ChargeOption()
bit [14:13] = 10⁽⁴⁾
70
88
105
t_WDI
Watchdog timeout period, ChargeOption()
bit [14:13] = 11⁽⁴⁾ (default)
140
175
210
UNIT
μs
ns
μs
μs
μs
μs
ns
ns
µs
μs
kHz
ms
ms
s
s
s
(3) Devices participating in a transfer timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a
timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave must
adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(4) User can adjust threshold via SMBus ChargeOption() REG0x12.
Figure 2. SMBus Communication Timing Waveforms
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