BQ24707 Datasheet, PDF (20/36 Pages) Texas Instruments – 1-4 Cell Li+ Battery SMBus Charge Controller With Independent Comparator and Advanced Circuit Protection

bq24707
bq24707A
SLUSA78B – JULY 2010 – REVISED MARCH 2011
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Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is
applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant
capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data
sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage
rating or nominal capacitance value in order to get the required value at the operating point.
Table 7. Suggested Component Values per Charge Current with a Default
750kHz Switching Frequency
Charge Current
2A
3A
4A
6A
8A
Output inductor Lo (µH)
6.8 or 8.2 5.6 or 6.8 3.3 or 4.7
3.3
2.2
Output capacitor Co (µF)
20
20
20
30
40
Sense resistor (mΩ)
10
10
10
10
10
The IC has three loops of regulation: input current, charge current, and charge voltage. The three loops are
brought together internally at the error amplifier. The maximum voltage of the three loops appears at the output
of the error amplifier EAO (see Figure 15). An internal saw-tooth ramp is compared to the internal error control
signal EAO to vary the duty-cycle of the converter. The ramp has an offset of 200mV in order to allow 0%
duty-cycle.
When the battery charge voltage approaches the input voltage, the EAO signal is allowed to exceed the
saw-tooth ramp peak in order to get a 100% duty-cycle. If voltage across the BTST and PHASE pins falls below
4.3V, a refresh cycle starts and the low-side n-channel power MOSFET is turned on to recharge the BTST
capacitor. It can achieve a duty-cycle of up to 99.5%.
Continuous Conduction Mode (CCM)
With sufficient charge current the IC inductor current never crosses zero, which is defined as continuous
conduction mode. The controller starts a new cycle with ramp coming up from 200mV. As long as EAO voltage is
above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO
voltage, the HSFET turns off and the low-side MOSFET (LSFET) turns on. At the end of the cycle, the ramp gets
reset and the LSFET turns off, ready for the next cycle. There is always break-before-make logic during the
transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the
body-diode of the low-side power MOSFET conducts the inductor current.
During CCM mode, the inductor current is always flowing and creates a fixed two-pole system. Having the
LSFET turn-on keeps the power dissipation low and allows safely charging at high currents.
Discontinuous Conduction Mode (DCM)
During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to zero, the
converter enters Discontinuous Conduction Mode. Every cycle, when the voltage across SRP and SRN falls
below 5mV (0.5A on 10mΩ), the under-current-protection comparator (UCP) turns off LSFET to avoid negative
inductor current, which may boost the system via the body diode of HSFET.
During the DCM mode the loop response automatically changes. It changes to a single pole system and the pole
is proportional to the load current.
Both CCM and DCM are synchronous operation with LSFET turn-on every clock cycle. If the average charge
current goes below 125mA on 10mΩ current sensing resistor or the battery voltage falls below 2.5V, the LSFET
keeps turn-off. The battery charger operates in non-synchronous mode and the current flows through the LSFET
body diode. During non-synchronous operation, the LSFET turns on only for refreshing pulse to charge BTST
capacitor. If the average charge current goes above 250mA on 10mΩ current sensing resistor, the LSFET exits
non-synchronous mode and enters synchronous mode to reduce LSFET power loss.
Input Over Current Protection (ACOC)
The IC cannot maintain the input current level if the charge current has been already reduced to zero. After the
system current continues increasing to the 1.66X of input current DAC set point (with 2.5ms blank out time),
IFAULT is pulled to low and the charge is disabled for 1.3s and will soft start again for charge if ACOC condition
goes away. If such failure is detected seven times in 90 seconds, charge will be latched off and an adapter
removal and system shut down (make ACDET < 0.6V to reset IC) is required to start charge again. After 90
seconds, the failure counter will be reset to zero to prevent latch off.
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