ADS58H40_14 Datasheet, PDF (7/60 Pages) Texas Instruments – Quad-Channel, 250-MSPS Receiver and Feedback ADC

ADS58H40
www.ti.com
SBAS589B – AUGUST 2012 – REVISED NOVEMBER 2012
TIMING REQUIREMENTS⁽¹⁾
Typical values are at +25°C, AVDD33 = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, sine-wave input clock, C_LOAD = 3.3 pF⁽²⁾, and
R_LOAD = 100 Ω⁽³⁾, unless otherwise noted.
Minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = +85°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t_A
Aperture delay
Aperture delay matching Between any two channels of the same device
0.7
1.2
±70
1.6
ns
ps
Variation of aperture delay
Between two devices at the same temperature and
DRVDD supply
±150
ps
t_J
Aperture jitter
Wake up time
Time to valid data after coming out of global power
down
Time to valid data after coming out of channel power
down
140
fs rms
100
µs
10
µs
Default latency in 11-bit mode
10
Output clock
cycles
Digital gain enabled
13
Output clock
cycles
Digital gain and offset correction enabled
14
Output clock
cycles
ADC latency⁽⁴⁾⁽⁵⁾
SNRBoost^3G+ (90-MHz BW) enabled alone
13
Output clock
cycles
SNRBoost^3G+ (90-MHz BW), digital gain, and offset
correction enabled
17
Output clock
cycles
SNRBoost^3G+ (45-MHz BW) enabled alone
15
Output clock
cycles
OUTPUT TIMING⁽⁶⁾
t_SU
Data setup time^(7)(8)(9)
t_H
Data hold time^(7)(8)(9)
LVDS bit clock duty cycle
SNRBoost^3G+ (45-MHz BW), digital gain, and offset
correction enabled
Data valid to CLKOUTxxP zero-crossing
CLKOUTxxP zero-crossing to data becoming invalid
Differential clock duty cycle (CLKOUTxxP –
CLKOUTxxM)
19
0.6
0.85
0.6
0.84
50%
Output clock
cycles
ns
ns
Input clock falling edge cross-over to output clock
t_PDI
Clock propagation delay⁽⁵⁾ falling edge cross-over, 184 MSPS ≤ sampling
0.25 × t_S + t_delay
ns
frequency ≤ 250 MSPS
t_delay
Delay time
Input clock falling edge cross-over to output clock
falling edge cross-over, 184 MSPS ≤ sampling
frequency ≤ 250 MSPS
6.9
8.65
10.5
ns
t_RISE,
t_FALL
t_CLKRISE,
t_CLKFALL
Data rise and fall time
Output clock rise and fall
time
Rise time measured from –100 mV to +100 mV
Rise time measured from –100 mV to +100 mV
0.1
ns
0.1
ns
(1) Timing parameters are ensured by design and characterization and are not tested in production.
(2) C_LOAD is the effective external single-ended load capacitance between each output pin and ground.
(3) R_LOAD is the differential load resistance between the LVDS output pair.
(4) ADC latency is given for channels B and D. For channels A and C, latency reduces by half of the output clock cycles.
(5) Overall latency = ADC latency + t_PDI.
(6) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
(7) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
(8) Note that these numbers are taken with delayed output clocks by writing the following registers: address A9h, value 02h; and address
ACh, value 60h. Refer to the Serial Interface Registers section. By default after reset, minimum setup time and minimum hold times are
520 ps each.
(9) The setup and hold times of a channel are measured with respect to the same channel output clock.
Table 2. LVDS Timings Across Lower Sampling Frequencies
SAMPLING FREQUENCY
(MSPS)
210
185
SETUP TIME (ns)
MIN
TYP
0.89
1.03
1.06
1.21
MAX
HOLD TIME (ns)
MIN
TYP
0.82
1.01
0.95
1.15
MAX
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