ADS58H40_14 Datasheet, PDF (38/60 Pages) Texas Instruments – Quad-Channel, 250-MSPS Receiver and Feedback ADC

ADS58H40
SBAS589B – AUGUST 2012 – REVISED NOVEMBER 2012
Register Address 62h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
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D0
SPECIAL MODE 15
Bits D[7:1]
Bit D0
D7
0
Always write '0'
SPECIAL MODE 15
Set the SPECIAL MODE[17:14] bits high to reduce the minimum functional clock speed
to 10 MSPS. Usage of these bits should be limited to functional checks only because
performance degrades when these bits are set high.
Register Address 92h (Default = 00h)
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
SPECIAL MODE 16
Bits D[7:1]
Bit D0
D7
0
Always write '0'
SPECIAL MODE 16
Set the SPECIAL MODE[17:14] bits high to reduce the minimum functional clock speed
to 10 MSPS. Usage of these bits should be limited to functional checks only because
performance degrades when these bits are set high.
Register Address 7Ah (Default = 00h)
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
SPECIAL MODE 17
Bits D[7:1]
Bit D0
Always write '0'
SPECIAL MODE 17
Set the SPECIAL MODE[17:14] bits high to reduce the minimum functional clock speed
to 10 MSPS. Usage of these bits should be limited to functional checks only because
performance degrades when these bits are set high.
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