ADS58H40_14 Datasheet, PDF (35/60 Pages) Texas Instruments – Quad-Channel, 250-MSPS Receiver and Feedback ADC

ADS58H40
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D7
EN FAST OVR THRESH
SBAS589B – AUGUST 2012 – REVISED NOVEMBER 2012
Register Address C4h (Default = 00h)
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
Bit D7
Bits D[6:0]
D7
0
EN FAST OVR THRESH
This bit enables the ADS58H40 to be programmed to select the fast OVR threshold.
Always write '0'
Register Address CFh (Default = 00h)
D6
D5
D4
D3
D2
D1
D0
0
0
0
SPECIAL MODE 0
0
0
0
Bits D[7:4]
Bit D3
Bits D[2:0]
Always write '0'
SPECIAL MODE 0
This bit must be set to ‘1’ when the SEL OFFSET CORR bit is selected.
Always write '0'
Register Address D4h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
SPECIAL MODE 1
0
0
0
0
0
0
0
Bit D7
Bits D[6:0]
SPECIAL MODE 1
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Always write '0'
Register Address D5h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
SPECIAL MODE 2
0
0
0
0
0
0
0
Bit D7
Bits D[6:0]
SPECIAL MODE 2
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Always write '0'
Register Address D6h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
SPECIAL MODE 3
0
0
0
0
0
0
0
Bit D7
Bits D[6:0]
SPECIAL MODE 3
Refer to Table 1 for optimal performance in a given frequency band and source
impedance.
Always write '0'
Copyright © 2012, Texas Instruments Incorporated
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