DAC34SH84_15 Datasheet, PDF (69/93 Pages) Texas Instruments – DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC)

www.ti.com
DAC34SH84
SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015
Register
Name
config30
Table 42. Register Name: config30 – Address: 0x1E, Default: 0x1111
Address
0x1E
Bit
Name
Function
15:12
11:8
7:4
3:0
syncsel_qmoffsetAB(3:0)
Selects the syncing source(s) of the AB data path double-buffered QMC offset
registers. A 1 in the bit enables the signal as a sync source. More than one sync
source is permitted.
MM Bit 15: sif_sync (via config31)
MM Bit 14: SYNC
MM Bit 13: OSTR
MM Bit 12: Auto-sync from register write
syncsel_qmoffsetCD(3:0)
Selects the syncing source(s) of the CD data path double-buffered QMC offset
registers. A 1 in the bit enables the signal as a sync source. More than one sync
source is permitted.
MM Bit 11: sif_sync (via config31)
MM Bit 10: SYNC
MM Bit 9: OSTR
MM Bit 8: Auto-sync from register write
syncsel_qmcorrAB(3:0)
Selects the syncing source(s) of the AB data path double buffered QMC correction
registers. A 1 in the bit enables the signal as a sync source. More than one sync
source is permitted.
MM Bit 7: sif_sync (via config31)
MM Bit 6: SYNC
MM Bit 5: OSTR
MM Bit 4: Auto-sync from register write
syncsel_qmcorrCD(3:0)
Selects the syncing source(s) of the CD data path double buffered QMC correction
registers. A 1 in the bit enables the signal as a sync source. More than one sync
source is permitted.
MM Bit 3: sif_sync (via config31)
MM Bit 2: SYNC
MM Bit 1: OSTR
MM Bit 0: Auto-sync from register write
Default
Value
0001
0001
0001
0001
Register
Name
config31
Table 43. Register Name: config31 – Address: 0x1F, Default: 0x1140
Address Bit
Name
0x1F
15:12 syncsel_mixerAB(3:0)
11:8 syncsel_mixerCD(3:0)
7:4 syncsel_nco(3:0)
3:2 syncsel_fifo_input(1:0)
1 sif_sync
0 Reserved
Function
Selects the syncing source(s) of the AB data path double buffered mixer
registers. A 1 in the bit enables the signal as a sync source. More than one sync
source is permitted.
MM Bit 15: sif_sync (via config31)
MM Bit 14: SYNC
MM Bit 13: OSTR
MM Bit 12: Auto-sync from register write
Selects the syncing source(s) of the CD data path double buffered mixer
registers. A 1 in the bit enables the signal as a sync source. More than one sync
source is permitted.
MM Bit 11: sif_sync (via config31)
MM Bit 10: SYNC
MM Bit 9: OSTR
MM Bit 8: Auto-sync from register write
Selects the syncing source(s) of the two NCO accumulators. A 1 in the bit
enables the signal as a sync source. More than one sync source is permitted.
MM Bit 7: sif_sync (via config31)
MM Bit 6: SYNC
MM Bit 5: OSTR
MM Bit 4: ISTR
Selects either the ISTR or SYNC LVDS signal to be routed to the internal
FIFO_ISTR path if syncsel_fifoin(3:0) is set to be ISTR (i.e. syncsel_fifoin(3:0) =
0010). In conjunction with config1 register bit(8), this allows flexibility of external
LVDS signal routing to the internal FIFO. The syncsel_fifo_input(1:0) can only
have one bit active at a time.
MM 00: external LVDS ISTR signal to internal FIFO_ISTR path
MM 01: external LVDS SYNC signal to internal FIFO_ISTR path
MM 10: external LVDS ISTR signal to internal FIFO_ISTR path
MM 11: external LVDS SYNC signal to internal FIFO_ISTR path
SIF created sync signal. Set to 1 to cause a sync and then clear to 0 to remove
it.
Reserved for factory use
Default
Value
0001
0001
0100
00
0
0
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: DAC34SH84
Submit Documentation Feedback
69