DAC34SH84_15 Datasheet, PDF (57/93 Pages) Texas Instruments – DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC)

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DAC34SH84
SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015
7.6 Register Map
Table 11. Register Map⁽¹⁾
Name
config0
config1
config2
config3
config4
config5
config6
config7
config8
config9
config10
config11
config12
config13
config14
config15
config16
config17
config18
config19
config20
config21
config22
config23
config24
config25
config26
config27
config28
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
Default
0x049C
0x040E
0x7000
0xF000
NA
NA
NA
0xFFFF
0x0000
0x8000
0x0000
0x0000
0x0400
0x0400
0x0400
0x0400
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
NA
0x0440
0x0020
0x0000
0x0000
(MSB)
Bit 15
Bit 14
qmc_
qmc_
offsetAB_ offsetCD_
ena
ena
Bit 13
qmc_
corrAB_
ena
Bit 12
qmc_
corrCD_
ena
Bit 11
iotest_
ena
reserved
reserved
64cnt_en oddeven_
a
parity
reserved
dacclk dataclk collision_
gone_ena gone_ena gone_ena
coarse_dac(3:0)
reserved
alarm_
from_
zerochk
reserved
alarms_from_fifo(2:0)
tempdata(7:0)
reserved reserved reserved
fifo_offset(2:0)
reserved reserved reserved
reserved reserved reserved
reserved reserved reserved reserved
cmix(3:0)
reserved reserved reserved reserved
output_delayAB(1:0) output_delayCD(1:0)
reserved reserved reserved reserved
reserved reserved reserved reserved
reserved
reserved
reserved
reserved
extref_
ena
reserved
pll_reset
pll_
ndivsync_
ena
pll_m(7:0)
pll_vco(5:0)
reserved
reserved
reserved
fuse_
sleep
reserved
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
interp(3:0)
fifo_ena
reserved
reserved
alarm_out_ alarm_out clkdiv_sync_ invsincAB_ invsincCD_
ena
pol
ena
ena
ena
parity_
ena
single_
dual_
parity
rev_
dacA_
dacB_
dacC_
dacD_
interface complement complement complement complement
alarm_
2away_
ena
alarm_
1away_
ena
alarm_
collision_
ena
reserved
reserved reserved reserved sif4_ena mixer_ena mixer_gain nco_ena
revbus
reserved
twos
reserved
reserved
alarm_
dacclk_
gone
alarm_
dataclk_
gone
reserved
iotest_results(15:0)
alarm_
output_
gone
alarm_
from_
iotest
reserved
alarm_
from_pll
alarm_
Aparity
reserved
alarms_mask(15:0)
qmc_offsetA(12:0)
qmc_offsetB(12:0)
qmc_offsetC(12:0)
qmc_offsetD(12:0)
qmc_gainA(10:0)
qmc_gainB(10:0)
qmc_gainC(10:0)
qmc_gainD(10:0)
qmc_phaseAB(11:0)
qmc_phaseCD(11:0)
phase_offsetAB(15:0)
phase_offsetCD(15:0)
phase_addAB(15:0)
phase_addAB(31:16)
phase_addCD(15:0)
phase_addCD(31:16)
alarm_
Bparity
alarm_
Cparity
sif_txenable
alarm_
Dparity
reserved
reserved
reserved
pll_ena
reserved
pll_cp(1:0)
pll_p(2:0)
pll_lfvolt(2:0)
reserved reserved
reserved reserved reserved
bias_
sleep
reserved
pll_n(3:0)
tsense_
sleep
pll_sleep
reserved
clkrecv_
sleep
pll_vcoitune(1:0)
sleepA
sleepB
reserved
reserved
reserved
sleepC
sleepD
(1) Unless otherwise noted, all reserved registers should be programmed to default values.
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