DAC34SH84_15 Datasheet, PDF (43/93 Pages) Texas Instruments – DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC)

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DAC34SH84
SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015
7.3.12 Parity Check Test
The DAC34SH84 has a parity check test that enables continuous validity monitoring of the data received by the
DAC. Parity check testing in combination with the data pattern checker offer an excellent solution for detecting
board assembly issues due to missing pad connections.
For the parity check test, an extra parity bit is added to the data bits to ensure that the total number of set bits
(bits with value 1) is even or odd. This simple scheme is used to detect single or any other odd number of data
transfer errors. Parity testing is implemented in the DAC34SH84 in two ways: 32-bit parity and dual 16-bit parity.
7.3.12.1 32-Bit Parity
In the 32-bit mode the additional parity bit is sourced to the parity input (PARITYP/N) for the 32-bit data transfer
into the DAB[15:0]P/N and DCD[15:0]P/N inputs. This mode is enabled by setting parity_ena = 1 and
single_dual_parity = 0 in register config1. The input parity value is defined to be the total number of logic 1s on
the 33-bit data bus – the DAB[15:0]P/N inputs, the DCD[15:0]P/N inputs, and the PARITYP/N input. This value,
the total number of logic 1s, must match the parity test selected in the oddeven_parity bit in register config1.
For example, if the oddeven_parity bit is set to 1 for odd parity, then the number of 1s on the 33-bit data bus
should be odd. The DAC will check the data transfer through the parity input. If the data received has odd
number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect.
The corresponding alarm for parity error will be set accordingly.
Figure 75 shows the simple XOR structure used to check word parity. Parity is tested independently for data
captured on both rising and falling edges of DATACLK (alarm_Aparity and alarm_Bparity, respectively). Testing
on both edges helps in determining a possible setup or hold issue. Both alarms are captured individually in
register config5.
PARITY
alarm_Aparity
DAB[15:0]
oddeven_parity
DCD[15:0]
Parity Block
alarm_Bparity
DATACLK
Figure 75. DAC34SH84 32-Bit Parity Check
B0458-02
7.3.12.2 Dual 16-Bit Parity
In the dual 16-bit mode, each 16-bit LVDS data bus input will be accompanied by a parity bit for error checking.
The DAB[15:0]P/N and ISTRP/N are one 17-bit data path, and the DCD[15:0]P/N and PARITYP/N are another
path. This mode is enabled by setting parity_ena = 1 and single_dual_parity = 1 in register config1. The input
parity value is defined to be the total number of logic 1s on each 17-bit data bus. This value, the total number of
logic 1s, must match the parity test selected in the oddeven_parity bit in register config1.
For example, if the oddeven_parity bit is set to 1 for odd parity, then the number of 1s on each 17-bit data bus
should be odd. The DAC will check the data transfer through the parity input. If the data received has odd
number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect.
The corresponding alarm for parity error will be set accordingly.
Figure 76 shows the simple XOR structure used to check word parity. Parity is tested independently for data
captured on both rising and falling edges of DATACLK for each data path (alarm_Aparity, alarm_Bparity,
alarm_Cparity, and alarm_Dparity, respectively). Testing on both edges and both data buses helps in
determining a possible setup or hold issue. All of the alarms are captured individually in register config5.
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