DAC34SH84_15 Datasheet, PDF (24/93 Pages) Texas Instruments – DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC)

DAC34SH84
SLAS808E – FEBRUARY 2012 – REVISED SEPTEMBER 2015
www.ti.com
SDENB
SCLK
SDIO
SDO
Instruction Cycle
Data Transfer Cycle
rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDENB
SCLK
SDIO
SDO
Data n
Data n – 1
t_d(Data)
Figure 50. Serial-Interface Read Timing Diagram
T0522-01
7.3.2 Data Interface
The DAC34SH84 has a 32-bit LVDS bus that accepts quad, 16-bit data in word-wide format. The quad, 16-bit
data can be input to the device using a dual-bus, 16-bit interface. The bus accepts LVDS transfer rates up to 1.5
GSPS, which corresponds to a maximum data rate of 750 MSPS per data channel. The default LVDS bus input
assignment is shown in Table 2.
Table 2. LVDS Bus Input Assignment
DATA PATHS
A and B
C and D
PINS
DAB[15..0]
DCD[15..0]
Data is sampled by the LVDS double-data-rate (DDR) clock DATACLK. Setup and hold requirements must be
met for proper sampling. A and C data are captured on the rising edge of DATACLK. B and D data are captured
on the falling edge of DATACLK.
For both input bus modes, a sync signal, either ISTR or SYNC, is required to sync the FIFO read and/or write
pointers.
The sync signal, either ISTR or SYNC, can be either a pulse or a periodic signal where the sync period
corresponds to multiples of eight samples. ISTR or SYNC is sampled by a rising edge in DATACLK. The pulse
duration t_{(ISTR_SYNC)} must be at least equal to one-half of the DATACLK period.
7.3.3 Data Format
The 16-bit data for channels A and B is interleaved in the form A₀[15:0], B₀[15:0], A₁[15:0], B₁[15:0], A₂[15:0]…
into the DAB[15:0]P/N LVDS inputs. Similarly, data for channels C and D is interleaved into the DCD[15:0]P/N
LVDS inputs. Data into the DAC34SH84 is formatted according to the diagram shown in Figure 51, where index
0 is the data LSB and index 15 is the data MSB.
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