AFE5808A_15 Datasheet, PDF (69/83 Pages) Texas Instruments – Ultrasound Analog Front-End

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AFE5808A
SLOS729D – OCTOBER 2011 – REVISED NOVEMBER 2015
In the 16/8/4 × ƒ_cw operations modes, low phase noise clock is required for 16/8/4 × ƒ_cw clocks (that is
CLKP_16X/ CLKM_16X pins) to maintain good CW phase noise performance. The 1 × ƒ_cw clock (that is
CLKP_1X/ CLKM_1X pins) is only used to synchronize the multiple AFE5808A chips and is not used for
demodulation. Thus 1 × ƒ_cw clock’s phase noise is not a concern. However, in the 1 × ƒ_cw operation mode, low
phase noise clocks are required for both CLKP_16X/ CLKM_16X and CLKP_1X/ CLKM_1X pins since both of
them are used for mixer demodulation. In general, higher slew rate clock has lower phase noise; thus clocks with
high amplitude and fast slew rate are preferred in CW operation. In the CMOS clock mode, 5-V CMOS clock can
achieve the highest slew rate.
Clock phase noise can be improved by a divider as long as the divider’s phase noise is lower than the target
phase noise. The phase noise of a divided clock can be improved approximately by a factor of 20logN dB where
N is the dividing factor of 16, 8, or 4. If the target phase noise of mixer LO clock 1׃_cw is 160 dBc/Hz at 1 kHz off
carrier, the 16 × ƒ_cw clock phase noise should be better than 160 – 20log16 = 136 dBc/Hz. TI’s jitter cleaners
LMK048X/CDCM7005/CDCE72010 exceed this requirement and can be selected for the AFE5808A device. In
the 4X/1X modes, higher quality input clocks are expected to achieve the same performance since N is smaller.
Thus the 16X mode is a preferred mode since it reduces the phase noise requirement for system clock design. In
addition, the phase delay accuracy is specified by the internal clock divider and distribution circuit. In the 16X
operation mode, the CW operation range is limited to 8 MHz due to the 16X CLK. The maximum clock frequency
for the 16X CLK is 128 MHz. In the 8X, 4X, and 1X modes, higher CW signal frequencies up to 15 MHz can be
supported with small degradation in performance (for example, the phase noise is degraded by 9 dB at 15 MHz,
compared to 2 MHz).
As the channel number in a system increases, clock distribution becomes more complex. It is not preferred to
use one clock driver output to drive multiple AFEs since the clock buffer’s load capacitance increases by a factor
of N. As a result, the falling and rising time of a clock signal is degraded. A typical clock arrangement for multiple
AFE5808A devices is shown in Figure 89. Each clock buffer output drives one AFE5808A device to achieve the
best signal integrity and fastest slew rate, that is better phase noise performance. When clock phase noise is not
a concern, for example, the 1 × ƒ_cw clock in the 16/8/4 × ƒ_cw operation modes, one clock driver output may excite
more than one AFE5808A device. Nevertheless, special considerations must be applied in such a clock
distribution network design. In typical ultrasound systems, TI recommends generating all clocks from a same
clock source, such as 16 × ƒ_cw, 1 × ƒ_cw clocks, audio ADC clocks, RF ADC clock, pulse repetition frequency
signal, frame clock, and so forth. By doing this, interference due to clock asynchronization can be minimized.
FPGA Clock/
Noisy Clock
n×16×CW Freq
LMK048X
CDCE72010
CDCM7005
16X CW
CLK
CDCLVP1208
LMK0030X
LMK01000
8 Synchronized
16 X CW CLKs
1X CW
CLK
CDCLVP1208
LMK0030X
LMK01000
8 Synchronized
1X CW CLKs
Figure 89. CW Clock Distribution
B0436-01
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