AFE5808A_15 Datasheet, PDF (32/83 Pages) Texas Instruments – Ultrasound Analog Front-End

AFE5808A
SLOS729D – OCTOBER 2011 – REVISED NOVEMBER 2015
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Table 1. Voltage-Controlled-Attenuator Noise vs Attenuation (continued)
ATTENUATION (dB)
0
ATTENUATOR INPUT REFERRED NOISE
(nV/√Hz)
2
8.3.3 Programmable Gain Amplifier
After the voltage controlled attenuator, a programmable gain amplifier (PGA) can be configured as 24 dB or 30
dB with a constant input referred noise of 1.75 nV/√Hz. The PGA structure consists of a differential voltage-to-
current converter with programmable gain, current clamp (bias control) circuits, a transimpedance amplifier with a
programmable low-pass filter, and a DC offset correction circuit. See Figure 62 for the simplified block diagram of
the PGA.
Current Clamp
To ADC
From attenuator
V/I
I/V
LPF
Current Clamp
DC Offset
Correction Loop
Figure 62. Simplified Block Diagram of PGA
Low input noise is always preferred in a PGA because its noise contribution should not degrade the ADC SNR
too much after the attenuator. At the minimum attenuation (used for small input signals), the LNA noise
dominates; at the maximum attenuation (large input signals), the PGA and ADC noise dominates. Thus 24-dB
gain of PGA achieves better SNR as long as the amplified signals can exceed the noise floor of the ADC.
The PGA current clamp circuit can be enabled (register 51) to improve the overload recovery performance of the
AFE. If we measure the standard deviation of the output just after overload, for 0.5 V V_CNTL, it is about 3.2 LSBs
in normal case (that is, the output is stable in about 1 clock cycle after overload). With the current clamp circuit
disabled, the value approaches 4 LSBs, meaning a longer time duration before the output stabilizes; however,
with the current clamp circuit enabled, there will be degradation in HD3 for PGA output levels > –2dBFS. For
example, for a –2-dBFS output level, the HD3 degrades by approximately 3 dB. To maximize the output dynamic
range, the maximum PGA output level can be above 2 V_PP even with the clamp circuit enabled; the ADC in the
AFE has excellent overload recovery performance to detect small signals right after the overload.
NOTE
In the low power and medium power modes, PGA_CLAMP is disabled for saving power if
51[7] = 0.
The AFE5808A device integrates an anti-aliasing filter in the form of a programmable low-pass filter (LPF) in the
transimpedance amplifier. The LPF is designed as a differential, active, 3rd order filter with a typical 18 dB-per-
octave roll-off. Programmable through the serial interface, the –1-dB frequency corner can be set to one of 10
MHz, 15 MHz, 20 MHz, and 30 MHz. The filter bandwidth is set for all channels simultaneously.
A selectable DC offset correction circuit is implemented in the PGA as well. This correction circuit is similar to the
one used in the LNA. The circuit extracts the DC component of the PGA outputs and feeds back to the PGA’s
complimentary inputs for DC offset correction. This DC offset correction circuit also has a high-pass response
with a cut-off frequency of 80 KHz.
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