AFE5808A_15 Datasheet, PDF (16/83 Pages) Texas Instruments – Ultrasound Analog Front-End

AFE5808A
SLOS729D – OCTOBER 2011 – REVISED NOVEMBER 2015
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7.7 Switching Characteristics
Typical values are at 25°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, differential clock, C_LOAD = 5
pF, R_LOAD = 100 Ω, 14 bit, sample rate = 65MSPS (unless otherwise noted). Minimum and maximum values are across the
full temperature range T_MIN = 0°C to T_MAX = 85°C with AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
ta
Aperture delay
The delay in time between the rising edge of the input sampling
clock and the actual time at which the sampling occurs
0.7
3
ns
Aperture delay
matching
Across channels within the same device
±150
ps
t_j
Aperture jitter
ADC latency
Default, after reset, or 0 x 2 [12] = 1, LOW_LATENCY = 1
450
Fs rms
11/8
Input
clock
cycles
t_delay
Data and frame clock Input clock rising edge (zero cross) to frame clock rising edge (zero
delay
cross) minus 3/7 of the input clock period (T).
3 5.4
7
ns
Δt_delay
Delay variation
At fixed supply and 20°C T difference. Device to device
–1
1 ns
t_RISE
t_FALL
Data rise time
Data fall time
Rise time measured from –100 to 100 mV, fall time measured from
0.14
100 mV to –100 mV, 10 MHz < f_CLKIN < 65 MHz
0.15
ns
t_FCLKRISE
t_FCLKFALL
Frame clock rise time
Frame clock fall time
Rise time measured from –100 mV to 100 mV, fall time measured
from 100 mV to –100 mV, 10 MHz < f_CLKIN < 65 MHz
0.14
0.15
ns
Frame clock duty cycle Zero crossing of the rising edge to zero crossing of the falling edge 48% 50% 52%
t_DCLKRISE
t_DCLKFALL
Bit clock rise time
Bit clock fall time
Bit clock duty cycle
Rise time measured from –100 to 100 mV, fall time measured from
0.13
100 mV to –100 mV, 10 MHz < f_CLKIN < 65 MHz
ns
0.12
Zero crossing of the rising edge to zero crossing of the falling edge 46%
10 MHz < f_CLKIN < 65 MHz
54%
(1) Timing parameters are ensured by design and characterization; not production tested.
7.8 Timing Requirements
Minimum values across full temperature range T_MIN = 0°C to T_MAX = 85°C, AVDD_5V =5 V, AVDD = 3.3 V, AVDD_ADC = 1.8
V, DVDD = 1.8 V
PARAMETER
DESCRIPTION
MIN TYP MAX UNIT
t₁
SCLK period
t₂
SCLK high time
t₃
SCLK low time
t₄
Data setup time
t₅
Data hold time
t₆
SEN fall to SCLK rise
t₇
Time between last SCLK rising edge to SEN rising edge
t₈
SDOUT delay
50
ns
20
ns
20
ns
5
ns
5
ns
8
ns
8
ns
12
20
28 ns
16
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