AFE5808A_15 Datasheet, PDF (49/83 Pages) Texas Instruments – Ultrasound Analog Front-End

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AFE5808A
SLOS729D – OCTOBER 2011 – REVISED NOVEMBER 2015
Table 4. Digital HPF –1-dB Corner Frequency vs K and Fs
k
40 MSPS
50 MSPS
65 MSPS
2
2780 kHz
3480 kHz
4520 kHz
3
1490 kHz
1860 kHz
2420 kHz
4
770 kHz
960 kHz
1250 kHz
8.6.2.6 LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
The low-frequency noise suppression mode is especially useful in applications where good noise performance is
desired in the frequency band of 0 MHz to 1 MHz (around DC). Setting this mode shifts the low-frequency noise
of the AFE5808A device to approximately Fs / 2, thereby moving the noise floor around DC to a much lower
value. Register bit 1[11] is used for enabling or disabling this feature. When this feature is enabled, power
consumption of the device increases by approximately 1 mW/CH.
8.6.2.7 LVDS_OUTPUT_RATE_2X: Address: 1[14]
The output data always uses a DDR format, with valid/different bits on the positive as well as the negative edges
of the LVDS bit clock, DCLK. The output rate is set by default to 1X (LVDS_OUTPUT_RATE_2X = 0), where
each ADC has one LVDS stream associated with it. If the sampling rate is low enough, two ADCs can share one
LVDS stream, thereby lowering the power consumption devoted to the interface. The unused outputs will output
zero. To avoid consumption from those outputs, no termination must not be connected to them. The distribution
on the used output pairs is done in the following way:
• Channel 1 and channel 2 come out on channel 3. Channel 1 comes out first.
• Channel 3 and channel 4 come out on channel 4. Channel 3 comes out first.
• Channel 5 and channel 6 come out on channel 5. Channel 5 comes out first.
• Channel 7 and channel 8 come out on channel 6. Channel 7 comes out first.
8.6.2.8 CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
Setting this bit to 1 enables the subtraction of the value on the corresponding OFFSET_CHx<9:0> (offset for
channel i) from the ADC output. The number is specified in 2s-complement format. For example,
OFFSET_CHx<9:0> = 11 1000 0000 means subtract 128. For OFFSET_CHx<9:0> = 00 0111 1111 the effect is
to subtract 127. In effect, both addition and subtraction can be performed. Note that the offset is applied before
the digital gain (see ADC_OUTPUT_FORMAT: Address: 4[3]). The whole data path is 2s-complement
throughout internally, with digital gain being the last step. Only when ADC_OUTPUT_FORMAT = 1 (straight
binary output format) is the 2s-complement word translated into offset binary at the end.
8.6.2.9 SERIALIZED_DATA_RATE: Address: 3[14:13]
LVDS Rate
Reg 3 [14:13]
Reg 4 [2:0]
Description
Table 5. Corresponding Register Settings
12 bit (6X DCLK)
11
010
2 LSBs removed
14 bit (7X DCLK)
00
000
N/A
16 bit (8X DCLK)
01
000
2 0s added at LSBs
8.6.2.10 TEST_PATTERN_MODES: Address: 2[15:13]
The AFE5808A device can output a variety of test patterns on the LVDS outputs. These test patterns replace the
normal ADC data output. The device may also be made to output 6 preset patterns:
1. Ramp: Setting Register 2[15:13] = 111 causes all the channels to output a repeating full-scale ramp pattern.
The ramp increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the
full-scale code, it returns back to zero code and ramps again.
2. Zeros: The device can be programmed to output all zeros by setting Register 2[15:13] = 110;
3. Ones: The device can be programmed to output all 1s by setting Register 2[15:13] = 100;
4. Deskew Patten: When 2[15:13] = 010; this mode replaces the 14-bit ADC output with the 01010101010101
word.
5. Sync Pattern: When 2[15:13] = 001, the normal ADC output is replaced by a fixed 11111110000000 word.
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