TMS320DM642_17 Datasheet, PDF (67/178 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

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PCI
HD[15:0]
16
HRDY, HINT
HCNTL0, HCNTL1,
HHWIL, HAS, HR/W,
HCS, HDS1, HDS2
MTXD[3:0], MTXEN
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
MDIO, MDCLK
HPI
(16-Bit)
EMAC
MDIO
STCLK ^(A)
VP0CLK0
VP0CLK1,
VP0CTL[2:0],
VP0D[19:10]
CLKR0, FSR0, DR0,
CLKS0, DX0, FSX0,
CLKX0
VP0
(10-Bit)
McBSP0
McASP0 Control
McASP0 Data
EMIFA
Clock
and
System
TIMER2
TMS320DM642
SPRS200N – JULY 2002 – REVISED OCTOBER 2010
64
AED[63:0]
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[7:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
CLKOUT4, CLKOUT6, PLLV
TIMER1
TIMER0
GP0
and
EXT_INT
I2C0
TINP1
TOUT1/LENDIAN
TINP0
TOUT0/MACEN
GP0[15:9, 3:0]
GP0[7:4]
SCL0
SDA0
CLKR1, FSR1, DR1,
CLKS1, DX1, FSX1,
CLKX1
McBSP1
VIC
VDAC/GP0[8]/PCI66
STCLK ^(A)
VP1CLK0
VP1CLK1,
VP1CTL[2:0],
VP1D[19:10]
VP1
(10-Bit)
VP2
(20-Bit)
STCLK ^(A)
VP2CLK0
VP2CLK1,
VP2CTL[2:0],
VP2D[19:0]
PERCFG Register Value: 0x0000 007E
Extenal Pins:
PCI_EN = 0
GP0[3]/PCIEEAI = 0 HD5 = 0
TOUT0/MAC_EN = 1
Shading denotes a peripheral module not available for this configuration.
A. STCLK supports all three video ports (VP2, VP1, and VP0).
Figure 3-7. Configuration Example B
(2 10-Bit Video Ports + 2 McBSPs + EMAC + MDIO + I2C0 + EMIF)
[Possible Video IP Phone Application]
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Device Configurations
67