TMS320DM642_17 Datasheet, PDF (146/178 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642
SPRS200N – JULY 2002 – REVISED OCTOBER 2010
5.14.3.3 VCLKIN Timing (Video Display Mode)
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Table 5-64. Timing Requirements for Video Display Mode for VPxCLKINx⁽¹⁾ (see Figure 5-59)
NO.
1 t_c(VKI)
Cycle time, VPxCLKINx
2 t_w(VKIH)
Pulse duration, VPxCLKINx high
3 t_w(VKIL)
Pulse duration, VPxCLKINx low
4 t_t(VKI)
Transition time, VPxCLKINx
(1) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.
–500
–600
–720
MIN MAX
9
4.1
4.1
3
UNIT
ns
ns
ns
ns
1
4
2
3
VPxCLKINx
4
Figure 5-59. Video Port Display VPxCLKINx Timing
5.14.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx
and VPxCLKOUTx (Video Display Mode)
Table 5-65. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to
VPxCLKINx and VPxCLKOUTx (see Figure 5-60)
NO.
13 t_{su(VCTLV-VKIH)}
Setup time, VPxCTLx valid before VPxCLKINx high
14 t_{h(VCTLV-VKIH)}
15 t_{su(VCTLV-VKOH)}
16 t_{h(VCTLV-VKOH)}
Hold time, VPxCTLx valid after VPxCLKINx high
Setup time, VPxCTLx valid before VPxCLKOUTx high⁽¹⁾
Hold time, VPxCTLx valid after VPxCLKOUTx high⁽¹⁾
(1) Assuming non-inverted VPxCLKOUTx signal.
–500
–600
–720
MIN
2.9
0.5
7.4
–0.9
MAX
UNIT
ns
ns
ns
ns
146 DM642 Peripheral Information and Electrical Specifications
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