TMS320DM642_17 Datasheet, PDF (41/178 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642
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SPRS200N – JULY 2002 – REVISED OCTOBER 2010
Table 2-4. Terminal Functions (continued)
SIGNAL
NAME
NO.
TYPE ⁽¹⁾
IPD/
IPU ⁽²⁾
DESCRIPTION
HD31/AD31/MRCLK⁽³⁾
G1
I
HD30/AD30/MCRS⁽³⁾
H3
I
HD29/AD29/MRXER⁽³⁾
G2
I
HD28/AD28/MRXDV⁽³⁾
J4
I
HD27/AD27/MRXD3⁽³⁾
H2
I
HD26/AD26/MRXD2⁽³⁾
J3
I
HD25/AD25/MRXD1⁽³⁾
J1
I
HD24/AD24/MRXD0⁽³⁾
K4
I
HD22/AD22/MTCLK⁽³⁾
L4
I
HD21/AD21/MCOL⁽³⁾
K2
I
HD20/AD20/MTXEN⁽³⁾
L3
O/Z
HD19/AD19/MTXD3⁽³⁾
L2
O/Z
HD18/AD18/MTXD2⁽³⁾
M4
O/Z
HD17/AD17/MTXD1⁽³⁾
M2
O/Z
HD16/AD16/MTXD0⁽³⁾
M3
O/Z
ETHERNET MAC (EMAC)
Host-port data (I/O/Z) [default] or EMAC transmit/receive or control pins (I) (O/Z)
HPI pin functions are default, see the Device Configurations section of this data
sheet. EMAC Media Independent I/F (MII) data, clocks, and control pins for
Transmit/Receive.
• MII transmit clock (MTCLK),
Transmit clock source from the attached PHY.
• MII transmit data (MTXD[3:0]),
Transmit data nibble synchronous with transmit clock (MTCLK).
• MII transmit enable (MTXEN),
This signal indicates a valid transmit data on the transmit data pins
(MTDX[3:0]).
• MII collision sense (MCOL)
Assertion of this signal during half-duplex operation indicates network
collision.
During full-duplex operation, transmission of new frames will not begin if this
pin is asserted.
• MII carrier sense (MCRS)
Indicates a frame carrier signal is being received.
• MII receive data (MRXD[3:0]),
Receive data nibble synchronous with receive clock (MRCLK).
• MII receive clock (MRCLK),
Receive clock source from the attached PHY.
• MII receive data valid (MRXDV),
This signal indicates a valid data nibble on the receive data pins
(MRDX[3:0]) and
• MII receive error (MRXER),
Indicates reception of a coding error on the receive data.
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