DAC3482 Datasheet, PDF (66/79 Pages) Texas Instruments – Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC3482
SLAS748A – MARCH 2011 – REVISED JUNE 2011
freq = f_CNO x 2^32 / 1228.8 = 429496730 = 0x1999999A
phaseaddAB(31:0) or phaseaddCD(31:0) = 0x1999999A
NCO SYNC = sif_sync
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EXAMPLE START-UP SEQUENCE
STEP
1
2
3
4
5
READ/WRITE
N/A
N/A
N/A
N/A
Write
6
Write
7
Write
8
Write
9
Write
10
Write
11
Write
12
Write
13
Write
14
Write
15
Write
16
Write
17
Write
18
Write
19
Write
20
Write
21
Write
22
Write
23
Write
24
Write
25
N/A
26
Read
27
Write
28
Read
Table 10. Example Start-Up Sequence Description
ADDRESS
N/A
N/A
N/A
N/A
0x00
0x01
0x02
0x03
0x07
0x08
0x09
0x0C
0x0D
0x10
0x12
0x14
0x15
0x18
0x19
0x1A
0x1B
0x1E
0x1F
0x20
N/A
0x18
0x05
0x05
VALUE
N/A
N/A
N/A
N/A
0xA19E
0x040E
0xF052
0xA000
0xD8FF
N/A
N/A
N/A
N/A
N/A
N/A
0x999A
0x1999
0x2C58
0x20F4
0x9000
0x0800
0x9191
0x4140
0x2400
N/A
N/A
0x0000
N/A
DESCRIPTION
Set TXENABLE Low
Power-up the device
Apply LVPECL DACCLKP/N for PLL reference clock
Toggle RESETB pin
QMC offset and correction enabled, 2x int, FIFO enabled, Alarm enabled,
clock divider sync enabled, inverse sinc filter enabled.
Single parity enabled, FIFO alarms enabled (2 away, 1 away, and collision).
Note: bit8 = ‘0’
Output shut-off when DACCLK gone, DATACLK gone, and FIFO collision.
Mixer block with NCO enabled, twos complement. Word wide interface.
Output current set to 20mAFS with internal reference and 1.28kohm R_BIAS
resistor.
Un-mask FIFO collision, DACCLK-gone, and DATACLK-gone alarms to the
Alarm output.
Program the desired channel I QMC offset value. (Causes Auto-Sync for
QMC Offset Block)
Program the desired FIFO offset value and channel Q QMC offset value.
Program the desired channel I QMC gain value.
Coarse mixer mode not used. Program the desired channel Q QMC gain
value.
Program the desired channel IQ QMC phase value. (Causes Auto-Sync
QMC Correction Block) Note : bit13 and bit12 = ‘1’
Program the desired channel IQ NCO phase offset value. (Causes
Auto-Sync for Channel IQ NCO Mixer)
Program the desired channel IQ NCO frequency value
Program the desired channel IQ NCO frequency value
PLL enabled, PLL N-dividers sync enabled, single charge pump, prescaler =
3.
M = 32, N = 16, PLL VCO bias tune = “01”
PLL VCO coarse tune = 36
Internal reference
QMC offset IQ and QMC correction IQ can be synced by sif_sync or
auto-sync from register write
Mixer IQ values synced by SYNCP/N. NCO accumulator synced by
SYNCP/N. FIFO data formatter synced by FRAMEP/N.
FIFO Input Pointer Sync Source = FRAME
FIFO Output Pointer Sync Source = OSTR (from PLL N-divider output)
Clock Divider Sync Source = OSTR
Provide all the LVDS DATA and DATACLK
Provide rising edge FRAMEP/N and rising edge SYNCP/N to sync the FIFO
input pointer and PLL N-dividers.
Read back pll_lfvolt(2:0). If the value is not optimal, adjust pll_vco(5:0) in
0x1A.
Clear all alarms in 0x05.
Read back all alarms in 0x05. Check for PLL lock, FIFO collision,
DACCLK-gone, DATACLK-gone, etc. Fix the error appropriately. Repeat
step 26 and 27 as necessary.
66
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