DAC3482 Datasheet, PDF (43/79 Pages) Texas Instruments – Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC)

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DATA
FRAME/
SYNC
DAC3482
SLAS748A – MARCH 2011 – REVISED JUNE 2011
Input Side
Clocked by DATACLK
I-Data, 16-Bit
Frame Align
Q-Data, 16-Bit
Write Pointer Reset
Initial
Position
0
32-Bit
1
2
3
4
5
6
7
Clock Handoff
FIFO:
2 x 16-Bits Wide
8-Samples deep
Sample 0
I₀[15:0], Q₀[15:0]
Sample 1
I₁[15:0], Q₁[15:0]
Sample 2
I₂[15:0], Q₂[15:0]
Sample 3
I₃[15:0], Q₃[15:0]
Sample 4
I₄[15:0], Q₄[15:0]
Sample 5
I₅[15:0], Q₅[15:0]
Sample 6
I₆[15:0], Q₆[15:0]
Sample 7
I₇[15:0], Q₇[15:0]
Output Side
Clocked by FIFO Out Clock
Word Wide Mode: DACCLK/2/Interpolation Factor
Byte Wide Mode: DACCLK/Interpolation Factor
0
1
32-Bit
2
3 _Initial
Position
4
5
6
7
16-Bit
FIFO I Output
16-Bit
FIFO Q Output
Read Pointer Reset
FIFO Reset
fifo_offset(2:0)
SM
syncsel_fifoout
OSTR
syncsel_fifoin
S (Single Sync Source Mode): Reset handoff from
input side to output side
M (Dual Sync Source Mode): OSTR resets read
pointer. Allows Multi-DAC synchronization
Figure 51. DAC3482 FIFO Block Diagram
B0451-01
Data is written to the device on the rising and falling edges of DATACLK. Each 32-bit wide sample (16-bit I-data
and 16-bit Q-data) is written into the FIFO at the address indicated by the write pointer. Similarly, data from the
FIFO is read by the FIFO Out Clock 32-bits at a time from the address indicated by the read pointer. The FIFO
Out Clock is generated internally from the DACCLK signal. Its rate is equal to DACCLK/2/Interpolation for
word-wide data transmission, or DACCLK/Interpolation for byte-wide data transmission. Each time a FIFO write
or FIFO read is done the corresponding pointer moves to the next address.
The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in
Figure 51. This offset gives optimal margin within the FIFO. The default read pointer location can be set to
another value using fifo_offset(2:0) in register config3 (address 4 by default). Under normal conditions data is
written-to and read-from the FIFO at the same rate and consequently the write and read pointer gap remains
constant. If the FIFO write and read rates are different, the corresponding pointers will be cycling at different
speeds which could result in pointer collision. Under this condition the FIFO attempts to read and write data from
the same address at the same time which will result in errors and thus must be avoided.
The write pointer sync source is selected by syncsel_fifoin(3:0) in register config32. In most applications either
FRAME or SYNC is used to reset the write pointer. Unlike DATA, the sync signal is latched only on the rising
edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position.
Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be
set to reset the read pointer as well. In this case, the FIFO Out clock will recapture the write pointer sync signal
to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of
the reset signal. This limits the precise control of the output timing and makes full synchronization of multiple
devices difficult.
Copyright © 2011, Texas Instruments Incorporated
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