DAC3482 Datasheet, PDF (60/79 Pages) Texas Instruments – Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC3482
SLAS748A – MARCH 2011 – REVISED JUNE 2011
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The first word in the test frame is determined by a rising edge transition in FRAME or SYNC, depending on the
syncsel_fifoin(3:0) setting in config32. At this transition, the pattern0 word should be input to the data pins.
Patterns 1 through 7 should follow sequentially on each edge of DATACLK (rising and falling). The sequence
should be repeated until the pattern checker test is disabled by setting iotest_ena back to 0. It is not necessary to
have a rising FRAME or SYNC edge aligned with every pattern0 word, just the first one to mark the beginning of
the series.
Start cycle again with optional rising edge of FRAME or SYNC
D[15:0]P/N
Pattern 0 Pattern 1 Pattern 2 Pattern 3 Pattern 4 Pattern 5 Pattern 6 Pattern 7
[15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0]
DATACLKP/N (DDR)
Sync
Option #1
FRAMEP/N
Sync
Option #2
SYNCP/N
Figure 76. IO Pattern Checker Data Transmission Format
T0528-01
The test mode determines if the 16-bit LVDS data D[15:0]P/N of all the patterns were received correctly by
comparing the received data against the data pattern key. If any of the 16-bit data D[15:0]P/N were received
incorrectly, the corresponding bits in iotest_results(15:0) in register config4 will be set to “1” to indicate bit error
location. Furthermore, the error condition will trigger the alarm_from_iotest bit in register config5 to indicate a
general error in the data interface. When data pattern checker mode is enabled, this alarm in register config5, bit
7 is the only valid alarm. Other alarms in register config5 are not valid and can be disregarded.
For instance, pattern0 is programmed to the default of 0x7A7A. If the received Pattern 0 is 0x7A7B, then bit 0 in
iotest_results(15:0) will be set to “1” to indicate an error in bit 0 location. The alarm_from_iotest will also be set to
“1” to report the data transfer error. The user can then narrow down the error from the alarm_from_iotest bit
location information and implement the fix accordingly.
The alarms can be cleared by writing 0x0000 to iotest_results(15:0) and “0” to alarm_from_iotest through the
serial interface. The serial interface will read back 0s if there are no errors or if the errors are cleared. The
corresponding alarm bit will remain a “1” if the errors remain.
Note that unless the unused data pins in byte-wide input format are forced to a known value the data pattern
checker is only available for the word-wide input data format. In byte-wide input format, the first 8-bits of the
iotest_pattern[0:7] in registers config37 through config44 will either need to be 0s or 1s for valid data pattern
checking.
It is recommended to enable the pattern checker and then run the pattern sequence for 100 or more complete
cycles before clearing the iotest_results(15:0) and alarm_from_iotest. This will eliminate the possibility of false
alarms generated during the setup sequence.
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