DAC3482 Datasheet, PDF (3/79 Pages) Texas Instruments – Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC)

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DEVICE INFORMATION
PINOUT
RKD Package
(Top View)
DAC3482
SLAS748A – MARCH 2011 – REVISED JUNE 2011
C1
LPF
PLLAVDD
OSTRP
OSTRN
DACCLKP
DACCLKN
CLKVDD
VFUSE
SYNCP
SYNCN
DIGVDD
IOVDD
D15P
D15N
D14P
D14N
DIGVDD
D13P
D13N
D12P
D12N
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
C2
DAC3482
88-WQFN 9mm x 9mm
C4
A33
B30
A32
B29
A31
B28
A30
B27
A29
B26
A28
B25
A27
B24
A26
B23
A25
B22
A24
B21
A23
BIASJ
RESETB
TXENABLE
ALARM
SCLK
SDENB
SDIO
SDO
PARITYN
PARITYP
DIGVDD
IOVDD
D0N
D0P
D1N
D1P
DIGVDD
D2N
D2P
D3N
D3P
C3
NAME
AVDD
PIN
NO.
A36, A37,
A38, A40,
A41, A42,
B31
ALARM
B29
BIASJ
A33
CLKVDD
A4
P0133-01
PIN FUNCTIONS
I/O
DESCRIPTION
I Analog supply voltage. (3.3 V)
CMOS output for ALARM condition. The ALARM output functionality is defined through the config7
O register. Default polarity is active low, but can be changed to active high via config0 alarm_out_pol
control bit.
O
Full-scale output current bias. For 30mA full-scale output current, connect 1.28kΩ to ground. Change
the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>
I
Internal clock buffer supply voltage. (1.2 V)
It is recommended to isolate this supply from DIGVDD and DACVDD.
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): DAC3482
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