TM4C1232C3PM Datasheet, PDF (656/1171 Pages) Texas Instruments – Tiva Microcontroller

General-Purpose Timers
10.4.4
10.4.5
■ In down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so
that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the
GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must
be counted.
■ In up-count mode, the timer counts from 0x0 to the value in the GPTMTnMATCHR and
GPTMTnPMR registers. Note that when executing an up-count, the value of the GPTMTnPR
and GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR.
6. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
8. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
When counting down in Input Edge-Count Mode, the timer stops after the programmed number of
edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and
repeat steps 4 through 8.
Input Edge Time Mode
A timer is configured to Input Edge Time mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3 and select a count direction by programming the TnCDIR bit.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPTMTnPR).
6. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
7. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
9. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timer n (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register and clearing
the TnILD bit in the GPTMTnMR register. The change takes effect at the next cycle after the write.
PWM Mode
A timer is configured to PWM mode using the following sequence:
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June 12, 2014
Texas Instruments-Production Data