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TM4C1232C3PM Datasheet, PDF (217/1171 Pages) Texas Instruments – Tiva Microcontroller
Tiva™ TM4C1232C3PM Microcontroller
the source for the module clock as well, which allows the transmit and receive FIFOs to continue
operation while the part is in Deep-Sleep. Figure 5-6 on page 217 shows how the clocks are selected.
Figure 5-6. Module Clock Selection
Clock Control Register
PIOSC
1
0
Baud Clock
System Clock
Deep Sleep
1
0
Module Clock
5.2.6.4
Additional deep-sleep modes are available that lower the power consumption of the SRAM and
Flash memory. However, the lower power consumption modes have slower deep-sleep and wake-up
times, see “Dynamic Power Management” on page 217 for more information.
Dynamic Power Management
In addition to the Sleep and Deep-Sleep modes and the clock gating for the on-chip modules, there
are several additional power mode options that allow the LDO, Flash memory, and SRAM into
different levels of power savings while in Sleep or Deep-Sleep modes. Note that these features may
not be available on all devices; the System Properties (SYSPROP) register provides information
on whether a mode is supported on a given MCU. The following registers provides these capabilities:
■ LDO Sleep Power Control (LDOSPCTL): controls the LDO value in Sleep mode
■ LDO Deep-Sleep Power Control (LDODPCTL): controls the LDO value in Deep-Sleep mode
■ LDO Sleep Power Calibration (LDOSPCAL): provides factory recommendations for the LDO
value in Sleep mode
■ LDO Deep-Sleep Power Calibration (LDODPCAL): provides factory recommendations for the
LDO value in Deep-Sleep mode
■ Sleep Power Configuration (SLPPWRCFG): controls the power saving modes for Flash memory
and SRAM in Sleep mode
■ Deep-Sleep Power Configuration (DSLPPWRCFG): controls the power saving modes for Flash
memory and SRAM in Deep-Sleep mode
■ Deep-Sleep Clock Configuration (DSLPCLKCFG): controls the clocking in Deep-Sleep mode
■ Sleep / Deep-Sleep Power Mode Status (SDPMST): provides status information on the various
power saving events
June 12, 2014
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