TM4C1232C3PM Datasheet, PDF (137/1171 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1232C3PM Microcontroller
Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284
Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288
Register 22: Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C
Note: This register can only be accessed from privileged mode.
The UNPENDn registers show which interrupts are pending and remove the pending state from
interrupts. Bit 0 of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of
UNPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2
corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to
Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of UNPEND4 (see page 138) corresponds to
Interrupt 128; bit 10 corresponds to Interrupt 138.
See Table 2-9 on page 93 for interrupt assignments.
Interrupt 0-31 Clear Pending (UNPEND0)
Base 0xE000.E000
Offset 0x280
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INT
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
INT
Type
Reset Description
RW 0x0000.0000 Interrupt Clear Pending
Value Description
0 On a read, indicates that the interrupt is not pending.
On a write, no effect.
1 On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
June 12, 2014
137
Texas Instruments-Production Data