TM4C1232C3PM Datasheet, PDF (609/1171 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1232C3PM Microcontroller
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on
the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 611). Write access
to this register is protected with the GPIOCR register. Bits in GPIOCR that are cleared prevent writes
to the equivalent bit in this register.
Important: The table below shows special consideration GPIO pins. Most GPIO pins are configured
as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
GPIOPUR=0, and GPIOPCTL=0). Special consideration pins may be programed to a
non-GPIO function or may have special commit controls out of reset. In addition, a
Power-On-Reset (POR) or asserting RST returns these GPIO to their original special
consideration state.
Table 9-8. GPIO Pins With Special Considerations
GPIO Pins
Default Reset GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL GPIOCR
State
PA[1:0]
UART0
0
0
0
0
0x1
1
PA[5:2]
PB[3:2]
SSI0
I²¹C0
0
0
0
0
0x2
1
0
0
0
0
0x3
1
PC[3:0]
JTAG/SWD
1
PD[7]
GPIO^a
0
PF[0]
GPIO^a
0
1
0
1
0x1
0
0
0
0
0x0
0
0
0
0
0x0
0
a. This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the
pin in the GPIOLOCK register and uncommitting it by setting the GPIOCR register.
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware signals including the GPIO pins that can function as
JTAG/SWD signals and the NMI signal. The commit control process must be followed
for these pins, even if they are programmed as alternate functions other than JTAG/SWD
or NMI; see “Commit Control” on page 588.
Note:
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the GPIO pins that
can be used as the four JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 1099
for pin numbers). Writes to protected bits of the GPIO Alternate Function Select
(GPIOAFSEL) register (see page 603), GPIO Pull Up Select (GPIOPUR) register (see
page 609), GPIO Pull-Down Select (GPIOPDR) register (see page 611), and GPIO Digital
Enable (GPIODEN) register (see page 614) are not committed to storage unless the GPIO
Lock (GPIOLOCK) register (see page 616) has been unlocked and the appropriate bits of
the GPIO Commit (GPIOCR) register (see page 617) have been set.
June 12, 2014
609
Texas Instruments-Production Data