DAC38RF80_017 Datasheet, PDF (65/155 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
8.3.17.3 JESD204B Modes, Interpolation and Clock phase Programming
Table 36 lists the register field values required for each JESD204B mode, interpolation mode and clock phase.
The register field addresses are listed in Table 37.
Table 36. Register Programming for JESD and Interpolation Mode
Mode
L-M-F-S-
Hd
1 TX/2TX
Inter
p
CLOCK
PHASES
(1-0)
6 11
82121/NA
8 11
12 11
16 11
6 10
8 11
10 11
42111/841
11
12
11
16 11
18 11
24 11
8 01
12 10
22210/442 ^{16 11}
10
18 11
20 11
24 11
12410/244 ^{16 01}
10
24 10
8 01
44210/882 ^{12 10}
10
16 11
24 11
24410/484 ^{16 01}
10
24 10
24310/483
10
24
11
INTERP
(4-0)
00011
00100
00110
01000
00011
00100
00101
00110
01000
01001
01100
00100
00110
01000
01001
01010
01100
01000
00110
00100
00110
01000
01100
01000
01100
Register Field Programming
CLKJESD_DI CLKJESD_OU
V
T_DIV
(3-0)
(3-0)
L_M1
(4-0)
F_M1
(7-0)
0110
0011
0111
1010
0100
0110
00111
0x00
1011
0111
0010
0011
0011
0100
0101
0101
0110
0110
00011
0x00
0111
0111
1001
1000
1010
1010
0001
0100
0010
0110
0011
0100
0111
1000
00001
0x01
0101
1001
0110
1010
0001
0110
0111
1010
00000
0x03
0001
0100
0010
0011
0110
0111
00011
0x01
0110
1010
0001
0010
0111
1010
00001
0x03
01100
0011
1010
00001
0x02
M_M1
(7-0)
0x01
0x01
0x01
0x01
0x03
0x03
0x03
S_M1
(4-0)
00001
00000
00000
00000
00000
00000
00000
N_M1/N’_M
HD
1
(4-0)
1
01111
1
01111
0
01111
0
01111
0
01111
0
01111
0
01011
Table 37. Register Field Addresses for JESD204B Modes, Interpolation and Clock Phase Programming
Register Field Name
INTERP
CLKJESD_DIV
CLKJESD_OUT_DIV
L_M1
F_M1
M_M1
S_M1
HD
N_M1
N_M1’ (NPRIME_M1)
JESD_PHASE_MODE
Register
MULTIDUC_CFG1
SerDes_CLK
JESD_K_L
JESD_RBD_F
JESD_M_S
Register Address
0x0A
0x25
0x4C
0x4B
0x4D
JESD_N_HD_SCR
0x4E
JESD_LN_EN
0x4A
All registers are paged!
Bit(s)
12-8
15-12
11-8
4-0
7-0
15-8
4-0
6
4-0
12-8
1-0
Hyperlink
8.5.13
8.5.28
8.5.47
8.5.46
8.5.48
8.5.49
8.5.45
Copyright © 2016–2017, Texas Instruments Incorporated
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