DAC38RF80_017 Datasheet, PDF (57/155 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
8.3.14 Error Counter
All receive channels include a 12-bit counter for accumulating pattern verification errors. This counter is
accessible via the ECOUNT IEEE1500 Char field. It is an essential part of the eye scan capability (see the Eye
Scan section).
The counter increments once for every cycle that the TESTFAIL bit is detected. The counter does not increment
when at its maximum value (i.e., all 1s). When an IEEE1500 capture is performed, the count value is loaded into
the ECOUNT scan elements (so that it can be scanned out), and the counter is then reset, provided NCOR is set
high.
ECOUNT can be used to get a measure of the bit error rate. However, as the error rate increases, it becomes
less accurate due to limitations of the pattern verification capabilities. Specifically, the pattern verifier checks
multiple bits in parallel (as determined by the Rx bus width), and it is not possible to distinguish between 1 or
more errors.
8.3.15 Eye Scan
All receive channels provide features which facilitate mapping the received data eye or extracting a symbol
response. A number of fields accessible via the IEEE1500 Char scan chain allow the required low level data to
be gathered. The process of transforming this data into a map of the eye or a symbol response must then be
performed externally, typically in software.
The basic principle used is as follows:
• Enable dedicated eye scan input samplers, and generate an error when the value sampled differs from the
normal data sample;
• Apply a voltage offset to the dedicated eye scan input samplers, to effectively reduce their sensitivity;
• Apply a phase offset to adjust the point in the eye that the dedicated eye scan data samples are taken;
• Reset the error counter to remove any false errors accumulated as a result of the voltage or phase offset
adjustments;
• Run in this state for a period of time, periodically checking to see if any errors have occurred;
• Change voltage and/or phase offset, and repeat.
Alternatively, the algorithm can be configured to optimize the voltage offset at a specified phase offset, over a
specified time interval.
Eye scan can be used in both synchronous and asynchronous systems, while receiving normal data traffic. The
IEEE1500 Char fields used to directly control eye scan and symbol response extraction are ES, ESWORD, ES
BIT SELECT, ESLEN, ESPO, ESVO, ESVO OVR, ESRUN and ESDONE. Eye scan errors are accumulated in
ECOUNT.
The required eyescan mode is selected via the ES field, as shown in Table 29. When enabled, only data from
the bit position within the 20-bit word specified via ES BIT SELECT is analyzed. In other words, only eye scan
errors associated with data output at this bit position will accumulate in ECOUNT. The maximum legal ES BIT
SELECT is 10011.
ES[3:0]
0000
0x01
0x10
0x11
0100
1x00
1001
1110
1010
1101
Table 29. Eye Scan Mode Selection
EFFECT
Disabled. Eye scan is disabled.
Compare. Counts mismatches between the normal sample and the eye scan sample if ES[2] = 0, and matches
otherwise.
Compare zeros. As ES = 0x01, but only analyses zeros, and ignores ones.
Compare ones. As ES = 0x01, but only analyses ones, and ignores zeroes.
Count ones. Increments ECOUNT when the eye scan sample is a 1.
Average. Adjusts ESVO to the average eye opening over the time interval specified by ESLEN. Analyses zeroes when
ES[2] = 0, and ones when ES[2]= 1.
Outer. Adjusts ESVO to the outer eye opening (i.e. lowest voltage zero, highest voltage 1) over the time interval
specified by ESLEN. 1001 analyses zeroes, 1110 analyses ones.
Inner. Adjusts ESVO to the inner eye opening (i.e. highest voltage zero, lowest voltage 1) over the time interval
specified by ESLEN. 1010 analyses zeroes, 1101 analyses ones.
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