DAC38RF80_017 Datasheet, PDF (134/155 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL

DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
8.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
Figure 157. PLL Configuration 1 Register (PLL_CONFIG1)
15
14
13
12
11
10
9
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
1
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 122. CONFIG1 Field Descriptions
Bit Field
15:8 PLL_M_M1
7:4 Reserved
3:0 PLL_VCO_RDAC
Type
R/W
R/W
R/W
Reset
0x03
0x0
0x8
Description
VCO feedback divider; divide by is 4(M+1)
Reserved
Controls the VCO amplitude
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8
x
R/W
0
0
R/W
8.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
Figure 158. PLL Configuration 2 Register (PLL_CONFIG2)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15
PLL_VCOSEL
14:8 PLL_VCO
7:6 Reserved
5:2 PLL_CP_ADJ
1
Reserved
0
Reserved
Table 123. PLL_CONFIG2 Field Descriptions
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1000000
000
0110
0
0
Description
Selects between two VCOs
0 = 5.9 GHz VCO(2 turn inductor in upper VCO)
1 = 8.9 GHz VCO (1 turn in the lower VCO)
VCO frequency range
Reserved
Adjusts the charge pump current; 0 to 1.55 mA in 50 µA steps.
Setting to 0000 will hold the LPF pin at 0 V
Reserved
Reserved. Always write 0
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