DAC3484_15 Datasheet, PDF (65/107 Pages) Texas Instruments – DAC3484 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

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DAC3484
SLAS749E – MARCH 2011 – REVISED NOVEMBER 2015
Programming (continued)
STEP
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Table 10. Example Start-Up Sequence Description (continued)
READ/WRITE
Write
Write
Write
Write
Write
ADDRESS
0x1A
0x1B
0x1E
0x1F
0x20
N/A
N/A
Read
Write
Read
0x18
0x05
0x05
Write
Write
Write
Write
Write
N/A
0x1F
0x00
0x1F
0x20
0x18
N/A
VALUE
0x9000
0x0800
0x9999
0x4440
0x2400
N/A
N/A
0x0000
N/A
0x4442
0xF29B
0x4448
0x0000
0x2458
N/A
DESCRIPTION
PLL VCO coarse tune = 36
Internal reference
QMC offset AB, QMC offset CD, QMC correction AB, and QMC correction
CD can be synced by sif_sync or auto-sync from register write
Mixer AB and CD values synced by SYNCP/N. NCO accumulator synced by
SYNCP/N.
FIFO Input Pointer Sync Source = ISTR FIFO Output Pointer Sync Source =
OSTR (from PLL N-divider output) Clock Divider Sync Source = OSTR
Provide all the LVDS DATA and DATACLK Provide rising edge FRAMEP/N
and rising edge SYNCP/N to sync the FIFO input pointer and PLL N-
dividers.
Read back pll_lfvolt(2:0). If the value is not optimal, adjust pll_vco(5:0) in
0x1A.
Clear all alarms in 0x05.
Read back all alarms in 0x05. Check for PLL lock, FIFO collision, DACCLK-
gone, DATACLK-gone, etc. Fix the error appropriately. Repeat step 34 and
35 as necessary.
Sync all the QMC blocks using sif_sync. These blocks can also be synced
via auto-sync through appropriate register writes.
Disable clock divider sync.
Set sif_sync to 0b for the next sif_sync event.
Disable FIFO input and output pointer sync.
Disable PLL N-dividers sync.
Set TXENABLE high. Enable data transmission.
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