DAC3484_15 Datasheet, PDF (30/107 Pages) Texas Instruments – DAC3484 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC3484
SLAS749E – MARCH 2011 – REVISED NOVEMBER 2015
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SDENB
SCLK
SDIO
SDO
Instruction Cycle
Data Transfer Cycle
rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDENB
SCLK
SDIO
SDO
Data n
Data n – 1
t_d(Data)
Figure 51. Serial Interface Read Timing Diagram
T0522-01
7.3.2 Data Interface
The DAC3484 has a 16-bit LVDS bus that accepts quad, 16-bit data either in word-wide or dual byte-wide
formats. The quad, 16-bit data can be input to the device using either a single-bus, 16-bit interface or a dual-bus,
8-bit interface. The selection between the two modes is done through 16bit_in in the config2 register. The LVDS
bus inputs in each mode are shown in Table 2.
Table 2. LVDS Bus Input Assignment
INPUT MODE
Word-wide
Byte-wide
PINS
D[15..0] → Data for paths A, B, C
and D
D[15..8] → Data for paths A and B
D[7..0] → Data for paths C and D
Data is sampled by the LVDS double data rate (DDR) clock DATACLK. Setup and hold requirements must be
met for proper sampling.
For both input bus modes, a sync signal, either FRAME or SYNC, can sync the FIFO read and/or write pointers.
In byte-wide mode the sync source is needed to establish the correct sample boundaries.
The sync signal, either FRAME or SYNC, can be either a pulse or a periodic signal where the sync period
corresponds to multiples of 8 samples. FRAME or SYNC is sampled by a rising edge in DATACLK. The pulse-
width t_{(FRAME_SYNC)} needs to be at least equal to 1/2 of the DATACLK period.
For both input bus mode, the value in FRAME sampled by the next falling edge in DATACLK can be used as a
block parity value. This feature is enabled by setting frame_parity_ena in register config1 to 1b. Refer to Parity
Check Test section for more detail
7.3.2.1 Word-Wide Format
The single-bus, 16-bit interface is selected by setting 16bit_in to 1b in the config2 register. In this mode the 16-bit
data for channels A, B, C and D is input word-wide interleaved in the form A₀, B₀, C₀, D₀, A1… into the
D[15:0]P/N LVDS bus. Data into the DAC3484 is formatted according to the diagram shown in Figure 52 where
index 0 is the data LSB and index 15 is the data MSB.
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