DAC3484_15 Datasheet, PDF (56/107 Pages) Texas Instruments – DAC3484 Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

DAC3484
SLAS749E – MARCH 2011 – REVISED NOVEMBER 2015
www.ti.com
R_SET
1.0
R_SET R_EQ 1.2
R_SET 4.988R_EQ
(2)
5. With R_EQ of two parallel, 135 Ω Z_T (or 67.5 Ω equivalent), R_SET is 332 Ω with standard 1% resistor value. I_EQ
is approximately 3 mA. The expected voltage at negative terminals of LVDS ports is approximately 1.0 V.
The differential LVDS voltage is 200 mV.
6. With same R_SET of 332 Ω, if the R_EQ has dropped to two parallel, 85 Ω Z_T (or 42.5 Ω equivalent), I_EQ is
approximately 3.2 mA. The expected voltage at negative terminals of LVDS port is approximately 1.06 V. The
differential LVDS voltage is 136 mV. As long as the static LVDS differential voltage is above 100 mV, the
LVDS port will register a logic HIGH value for the data.
7.3.16 CMOS Digital Inputs
Figure 84 shows a schematic of the equivalent CMOS digital inputs of the DAC3484. SDIO, SCLK, SLEEP and
TXENABLE have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC3484.
See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to
100kΩ.
IOVDD
IOVDD
SDIO
SCLK
SLEEP
TXENABLE
100 kΩ
400 Ω
Internal
Digital In
100 kΩ
SDENB
RESETB
400 Ω
Internal
Digital In
GND
Figure 84. CMOS Digital Equivalent Input
GND
S0027-03
7.3.17 Reference Operation
The DAC3484 uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-
scale output current is set by applying an external resistor R_BIAS to pin BIASJ. The bias current I_BIAS through
resistor R_BIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale
output current equals 64 times this bias current and can thus be expressed as:
IOUT_FS = 64 x I_BIAS = 64 x (V_EXTIO / R_BIAS ) / 2
The DAC3484 has a 4-bit coarse gain control coarse_dac(3:0) in the config3 register. Using gain control, the
IOUT_FS can be expressed as:
IOUT_FS = (coarse_dac + 1)/16 x I_BIAS x 64 = (coarse_dac + 1)/16 x (V_EXTIO / R_BIAS) / 2 x 64
where V_EXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of
1.2 V. This reference is active when extref_ena = 0b in config27. An external decoupling capacitor C_EXT of 0.1 µF
should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be
used for external reference operation. In that case, an external buffer with high impedance input should be
applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be
disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor C_EXT may hence
be omitted. Terminal EXTIO thus serves as either input or output node.
The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor R_BIAS or changing
the externally applied reference voltage.
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