LM3S1627 Datasheet, PDF (626/719 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Pulse Width Modulator (PWM)
Register 53: PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804
Register 54: PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884
Register 55: PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904
Along with the PWMnFLTSTAT1 register, this register provides status regarding the fault condition
inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT0 register
are read-only (RO) and provide the current state of the FAULTn inputs.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT0 register are
read / write 1 to clear (R/W1C) and provide a latched version of the FAULTn inputs. In this mode,
the register bits are cleared by writing a 1 to a set bit. The FAULTn inputs are recorded after their
sense is adjusted in the generator.
The contents of this register can only be written if the fault source extensions are enabled (the
FLTSRC bit in the PWMnCTL register is set).
PWM0 Fault Status 0 (PWM0FLTSTAT0)
Base 0x4002.8000
Offset 0x804
Type -, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FAULT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
-
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
FAULT0
Type
RO
-
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Input 0
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the FAULT0 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is R/W1C and
represents a sticky version of the FAULT0 input signal after the logic
sense adjustment.
■ If FAULT0 is set, the input transitioned to the active state previously.
■ If FAULT0 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■ The FAULT0 bit is cleared by writing it with the value 1.
626
November 17, 2011
Texas Instruments-Production Data