CC430F613 Datasheet, PDF (60/120 Pages) Texas Instruments – MSP430 SoC with RF Core

CC430F613x
CC430F612x
CC430F513x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS554E – MAY 2009 – REVISED NOVEMBER 2010
www.ti.com
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note ⁽¹⁾, Figure 17 and Figure 18)
PARAMETER
TEST CONDITIONS
PMMCOR
EVx
V_CC
MIN TYP
t_STE,LEAD STE lead time, STE low to clock
1.8 V
11
0
3.0 V
8
2.4 V
7
3
3.0 V
6
t_STE,LAG
STE lag time, Last clock to STE
high
1.8 V
3
0
3.0 V
3
2.4 V
3
3
3.0 V
3
t_STE,ACC
STE access time, STE low to
SOMI data out
1.8 V
0
3.0 V
2.4 V
3
3.0 V
t_STE,DIS
STE disable time, STE high to
SOMI high impedance
1.8 V
0
3.0 V
2.4 V
3
3.0 V
t_SU,SI
SIMO input data setup time
1.8 V
5
0
3.0 V
5
2.4 V
2
3
3.0 V
2
t_HD,SI
SIMO input data hold time
1.8 V
5
0
3.0 V
5
2.4 V
5
3
3.0 V
5
t_VALID,SO
SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
C_L = 20 pF
1.8 V
0
3.0 V
2.4 V
3
3.0 V
t_HD,SO
SOMI output data hold time⁽³⁾ C_L = 20 pF
1.8 V
18
0
3.0 V
12
2.4 V
10
3
3.0 V
8
MAX UNIT
ns
ns
66
ns
50
36
30
30
ns
23
16
13
ns
ns
ns
ns
76
ns
60
44
ns
40
ns
ns
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(USCI), t_{SU,MI(Master)} + t_{VALID,SO(USCI)}).
For the master's parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 15 and Figure 16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 15
and Figure 16.
60
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