AM1808_12 Datasheet, PDF (60/262 Pages) Texas Instruments – ARM Microprocessor

AM1808
SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
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• Special case settings for peripherals:
– Locking of PLL controller settings
– Default burst sizes for EDMA3 transfer controllers
– Selection of the source for the eCAP module input capture (including on chip sources)
– McASP AMUTEIN selection and clearing of AMUTE status for the McASP
– Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
– Clock source selection for EMIFA
– DDR2 Controller PHY settings
– SATA PHY power management controls
• Selects the source of emulation suspend signal (from ARM) of peripherals supporting this function.
Many registers are accessible only by a host (ARM) when it is operating in its privileged mode. (ex. from
the kernel, but not from user space code).
Table 3-1. System Configuration (SYSCFG) Module Register Access
Register Address
0x01C1 4000
0x01C14008
0x01C1400C
0x01C14010
0x01C14014
0x01C1 4020
0x01C1 4038
0x01C1 403C
0x01C1 4040
0x01C1 4044
0x01C1 40E0
0x01C1 40E4
0x01C1 40E8
0x01C1 40EC
0x01C1 40F0
0x01C1 40F4
0x01C1 40F8
0x01C1 4110
0x01C1 4114
0x01C1 4118
0x01C1 4120
0x01C1 4124
0x01C1 4128
0x01C1 412C
0x01C1 4130
0x01C1 4134
0x01C1 4138
0x01C1 413C
0x01C1 4140
0x01C1 4144
0x01C1 4148
0x01C1 414C
0x01C1 4150
Register Name
REVID
DIEIDR0
DIEIDR1
DIEIDR2
DIEIDR3
BOOTCFG
KICK0R
KICK1R
HOST0CFG
HOST1CFG
IRAWSTAT
IENSTAT
IENSET
IENCLR
EOI
FLTADDRR
FLTSTAT
MSTPRI0
MSTPRI1
MSTPRI2
PINMUX0
PINMUX1
PINMUX2
PINMUX3
PINMUX4
PINMUX5
PINMUX6
PINMUX7
PINMUX8
PINMUX9
PINMUX10
PINMUX11
PINMUX12
Register Description
Revision Identification Register
Device Identification Register 0
Device Identification Register 1
Device Identification Register 2
Device Identification Register 3
Boot Configuration Register
Kick 0 Register
Kick 1 Register
Host 0 Configuration Register
Host 1 Configuration Register
Interrupt Raw Status/Set Register
Interrupt Enable Status/Clear Register
Interrupt Enable Register
Interrupt Enable Clear Register
End of Interrupt Register
Fault Address Register
Fault Status Register
Master Priority 0 Registers
Master Priority 1 Registers
Master Priority 2 Registers
Pin Multiplexing Control 0 Register
Pin Multiplexing Control 1 Register
Pin Multiplexing Control 2 Register
Pin Multiplexing Control 3 Register
Pin Multiplexing Control 4 Register
Pin Multiplexing Control 5 Register
Pin Multiplexing Control 6 Register
Pin Multiplexing Control 7 Register
Pin Multiplexing Control 8 Register
Pin Multiplexing Control 9 Register
Pin Multiplexing Control 10 Register
Pin Multiplexing Control 11 Register
Pin Multiplexing Control 12 Register
Register Access
—
—
—
—
—
Privileged mode
Privileged mode
Privileged mode
—
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
60
Device Configuration
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