AM1808_12 Datasheet, PDF (14/262 Pages) Texas Instruments – ARM Microprocessor

AM1808
SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
www.ti.com
2.5 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
2.5.1 Pin Map (Bottom View)
The following graphics show the bottom view of the ZCE and ZWT packages pin assignments in four
quadrants (A, B, C, and D). The pin assignments for both packages are identical.
1
2
3
4
5
6
7
8
9
10
VP_DOUT[0]/
LCD_D[0]/
W
UPP_XD[8]/
GP7[8]/
PRU1_R31[8]
VP_DOUT[1]/
LCD_D[1]/
UPP_XD[9]/
GP7[9]/
PRU1_R31[9]
VP_DOUT[2]/
LCD_D[2]/
UPP_XD[10]/
GP7[10]/
PRU1_R31[10]
DDR_A[10]
DDR_A[6]
DDR_A[2]
DDR_CLKN
DDR_CLKP
DDR_RAS
DDR_D[15]
W
VP_DOUT[3]/
VP_DOUT[4]/
VP_DOUT[5]/
LCD_D[3]/
V
UPP_XD[11]/
LCD_D[4]/
UPP_XD[12]/
LCD_D[5]/
UPP_XD[13]/
GP7[11]/
GP7[12]/
GP7[13]/
PRU1_R31[11]
PRU1_R31[12]
PRU1_R31[13]
DDR_A[12]
VP_DOUT[6]/
VP_DOUT[7]/
LCD_D[6]/
U
UPP_XD[14]/
LCD_D[7]/
UPP_XD[15]/
GP7[14]/
GP7[15]/
PRU1_R31[14]
PRU1_R31[15]
VP_DOUT[8]/
LCD_D[8]/
UPP_XD[0]/
GP7[0]/
BOOT[0]
DDR_A[8]
VP_DOUT[9]/
VP_DOUT[10]/
VP_DOUT[11]/
LCD_D[9]/
LCD_D[10]/
LCD_D[11]/
T
UPP_XD[1]/
GP7[1]/
UPP_XD[2]/
GP7[2]/
UPP_XD[3]/
GP7[3]/
BOOT[1]
BOOT[2]
BOOT[3]
DDR_A[11]
DDR_A[5]
DDR_A[4]
DDR_A[13]
DDR_A[3]
DDR_A[7]
DDR_A[9]
DDR_CKE
DDR_BA[0]
DDR_CS
DDR_D[13]
V
DDR_A[0]
DDR_BA[2]
DDR_CAS
DDR_D[12]
U
DDR_A[1]
DDR_WE
DDR_BA[1]
DDR_D[10]
T
VP_DOUT[12]/
VP_DOUT[13]/
VP_DOUT[14]/
LCD_D[12]/
R
UPP_XD[4]/
GP7[4]/
BOOT[4]
LCD_D[13]/
UPP_XD[5]/
GP7[5]/
BOOT[5]
LCD_D[14]/
UPP_XD[6]/
GP7[6]/
BOOT[6]
DVDD3318_C
LCD_AC_ENB_CS/
GP6[0]/
PRU1_R31[28]
DDR_VREF
DDR_DVDD18
DDR_DVDD18
DDR_DVDD18
DDR_DQM[1]
R
P
SATA_VDD
SATA_VDD
SATA_VDDR
VP_DOUT[15]/
LCD_D[15]/
UPP_XD[7]/
GP7[7]/
BOOT[7]
DVDD3318_C
DVDD3318_C
DDR_DVDD18
DDR_DVDD18
DDR_DVDD18
DDR_DVDD18
P
N
SATA_REFCLKN SATA_REFCLKP
SATA_REG
SATA_VDD
VSS
DDR_DVDD18
RVDD
CVDD
DDR_DVDD18
DDR_DVDD18
N
M
SATA_VSS
SATA_VDD
NC_M3
VSS
VSS
VSS
VSS
CVDD
CVDD
VSS
M
L
SATA_RXP
SATA_RXN
SATA_VSS
DVDD3318_C
VSS
DVDD18
VSS
VSS
VSS
VSS
L
K
SATA_VSS
SATA_VSS
VP_CLKOUT2/
MMCSD1_DAT[2]/
PRU1_R30[2]/
GP6[3]/
PRU1_R31[3]
VP_CLKOUT3/
PRU1_R30[0]/
GP6[1]/
PRU1_R31[1]
DVDD18
CVDD
VSS
VSS
VSS
VSS
K
1
2
3
4
5
6
7
8
9
10
AB
DC
Figure 2-1. Pin Map (Quad A)
14
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