ADS54J60 Datasheet, PDF (60/76 Pages) Texas Instruments – Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter

ADS54J60
SBAS706B – APRIL 2015 – REVISED AUGUST 2015
7.5.2.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)
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Figure 120. Register 16h
7
6
5
4
0
0
0
0
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
3
0
W-0h
2
0
W-0h
1
0
JESD PLL MODE
R/W-0h
Table 58. Register 16h Field Descriptions
Bit Field
7-2 0
1-0 JESD PLL MODE
Type
W
R/W
Reset
0h
0h
Description
Must write 0
These bits select the JESD PLL multiplication factor and must
match the JESD MODE setting.
00 = 20X mode, four lanes per ADC
01 = Not used
10 = 40X mode, two lanes per ADC
11 = Not used
7.5.2.6.3 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
Figure 121. Register 1Ah
7
6
5
4
0
0
0
0
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
3
0
W-0h
2
0
W-0h
1
FOVR CHA
R/W-0h
0
0
W-0h
Bit Field
7-2 0
1
FOVR CHA
0
0
Table 59. Register 1Ah Field Descriptions
Type
W
R/W
Reset
0h
0h
W
0h
Description
Must write 0
Outputs FOVR signal for channel A on the PDN pin. FOVR CHA
EN (register 1Bh, bit 3) must be enabled.
0 = Normal operation
1 = FOVR on the PDN pin
Must write 0
60
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