ADS54J60 Datasheet, PDF (1/76 Pages) Texas Instruments – Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter

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ADS54J60
SBAS706B – APRIL 2015 – REVISED AUGUST 2015
ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter
1 Features
•1 16-Bit Resolution, Dual-Channel, 1-GSPS ADC
• Noise Floor: –159 dBFS/Hz
• Spectral Performance (f_IN = 170 MHz at –1 dBFS):
– SNR: 70 dBFS
– NSD: –157 dBFS/Hz
– SFDR: 86 dBc (Including Interleaving Tones)
– SFDR: 96 dBc (Except HD2, HD3, and
Interleaving Tones)
• Spectral Performance (f_IN = 350 MHz at –1 dBFS):
– SNR: 67.5 dBFS
– NSD: –154.5 dBFS/Hz
– SFDR: 75 dBc
– SFDR: 85 dBc (Except HD2, HD3, and
Interleaving Tones)
• Channel Isolation: 100 dBc at f_IN = 170 MHz
• Input Full-Scale: 1.9 V_PP
• Input Bandwidth (3 dB): 1.2 GHz
• On-Chip Dither
• Integrated Wideband DDC Block
• JESD204B Interface with Subclass 1 Support:
– 2 Lanes per ADC at 10.0 Gbps
– 4 Lanes per ADC at 5.0 Gbps
– Support for Multi-Chip Synchronization
• Power Dissipation: 1.35 W/ch at 1 GSPS
• VQFNP-72 Package (10 mm × 10 mm)
3 Description
The ADS54J60 is a low-power, wide-bandwidth, 16-
bit, 1.0-GSPS, dual-channel, analog-to-digital
converter (ADC). Designed for high signal-to-noise
ratio (SNR), the device delivers a noise floor of
–159 dBFS/Hz for applications aiming for highest
dynamic range over a wide instantaneous bandwidth.
The device supports the JESD204B serial interface
with data rates up to 10 Gbps, supporting two or four
lanes per ADC. The buffered analog input provides
uniform input impedance across a wide frequency
range while minimizing sample-and-hold glitch
energy. Each ADC channel optionally can be
connected to a wideband digital down-converter
(DDC) block. The ADS54J60 provides excellent
spurious-free dynamic range (SFDR) over a large
input frequency range with very low power
consumption.
The JESD204B interface reduces the number of
interface lines, allowing high system integration
density. An internal phase-locked loop (PLL)
multiplies the ADC sampling clock to derive the bit
clock that is used to serialize the 16-bit data from
each channel.
PART NUMBER
ADS54J40
ADS54J60
Device Information
SPEED GRADE
(MSPS)
RESOLUTION
(Bits)
1000
14
1000
16
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• Radar and Antenna Arrays
• Broadband Wireless
• Cable CMTS, DOCSIS 3.1 Receivers
• Communications Test Equipment
• Microwave Receivers
• Software Defined Radio (SDR)
• Digitizers
FFT for 170 MHz Input Signal
(SNR = 69.8 dBFS; SFDR = 88 dBc;
IL Spur = 86 dBc; Non HD2, HD3 Spur = 89 dBc)
0
-20
-40
-60
-80
-100
-120
0
100
200
300
400
Input Frequency (MHz)
500
D003
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.