TLC2942_06 Datasheet, PDF (6/29 Pages) Texas Instruments – HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
PFD output control
A high level on PFD INHIBIT places the PFD OUT in the high-impedance state and the PFD stops phase
detection as shown in Table 4 and Table 5. A high level on PFD INHIBIT also can be used as the power-down
mode for the PFD.
PFD INHIBIT1
Low
High
Table 4. PFD1 Inhibit Function
DETECTION
Active
Stop
PFD OUT1
Active
Hi-Z
PFD1 IDD
Normal
Power Down
Table 5. PFD2 Inhibit Function Table
PFD INHIBIT2
Low
High
DETECTION
Active
Stop
PFD OUT2
Active
Hi-Z
PFD2 IDD
Normal
Power Down
schematics
VCO block schematic (VCO1, VCO2)
RBIAS
Ring Oscillator
Bias
Circuit
VCOIN1,
VCOIN2
(VCO control)
VCOINHIBIT
PFD block schematic (PFD1, PFD2)
FIN – A
FIN – B
PFD INHIBIT
Detector
VCO
Output
Charge Pump
VDD
PFD OUT
1/2
M
U
X
VCO OUT1,
VCO OUT2
SELECT1,2
6
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265