TLC2942_06 Datasheet, PDF (11/29 Pages) Texas Instruments – HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO1, VCO2 operating characteristics, V_DD = 5 V, T_A = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
fosc
Operating oscillation frequency
RBIAS1, RBIAS2 = 2.2 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD
32
41
50 MHz
ts(fosc)
Time to stable oscillation
See Note 8
10 µs
tr
Rise time
tf
Fall time
Duty cycle at VCO OUT
CL = 15 pF, See Figure 3
CL = 50 pF, See Figure 3
CL = 15 pF, See Figure 3
CL = 50 pF, See Figure 3
RBIAS1, RBIAS2 = 2.2 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD
5.5
10
ns
8
5
10
ns
6
45% 50% 55%
α_(fosc)
Temperature coefficient of oscillation frequency
RBIAS1, RBIAS2 = 2.2 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD,
Tope = –20°C to 75°C
0.06
%/°C
kSVS(fosc)
Supply voltage coefficient of oscillation fre-
quency
RBIAS1, RBIAS2 = 2.2 kΩ,
VCOIN1, VCOIN2 = 2.5 V,
VDD = 4.75 V to 5.25 V
0.006
%/mV
Jitter absolute (see Note 9)
RBIAS1 = 3.3 kΩ
100
ps
NOTES: 8. The time period to stabilize the VCO oscillation frequency after VCOINHIBIT is changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 9. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD1, PFD2 operating characteristics, V_DD = 5 V, T_A = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
fmax Maximum operating frequency
40
tPLZ
PFD output disable time from low level
tPHZ
tPZL
PFD output disable time from high level
PFD output enable time to low level
See Figures 4 and 5 and Table 4
tPZH PFD output enable time to high level
tr
Rise time
tf
Fall time
CL = 15 pF, See Figure 4
TYP MAX UNIT
MHz
21
40
ns
20
40
7.3
20
ns
6.5
20
2.3
10 ns
1.7
10 ns
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