TLC2942_06 Datasheet, PDF (3/29 Pages) Texas Instruments – HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
Terminal Functions
TERMINAL
I/
NAME
NO. ^O
DESCRIPTION
BIAS1
37
I VCO1 bias supply. An external resistor (RBIAS1) between VCO VDD1 and BIAS1 supplies bias for adjusting
the oscillation frequency range.
BIAS2
25
I VCO2 bias supply. An external resistor (RBIAS2) between VCO VDD2 and BIAS2 supplies bias for adjusting
the oscillation frequency range.
FIN–A1
FIN–A2
4
I Input reference frequency 1. The frequency f(REF IN)1 is applied to FIN-A1.
16
I Input reference frequency 2. The frequency f(REF IN)2 is applied to FIN-A2.
FIN–B1
5
I Input for VCO1 external counter output frequency f(FIN-B)1. FIN-B1 is nominally provided from the external
counter (see Figure 28).
FIN–B2
17
I Input for VCO2 external counter output frequency f(FIN-B)2. FIN-B2 is nominally provided from the external
counter (see Figure 28).
GND
8, 12,
27,31
Ground
LOGIC VDD1
1
Logic1 supply voltage. LOGIC VDD1 supplies voltage to internal logic 1. LOGIC VDD1 should be separate
from the other supply lines to reduce cross-coupling between power supplies.
LOGIC VDD2
13
Logic2 supply voltage. LOGIC VDD2 supplies voltage to internal logic 2. LOGIC VDD2 should be separate
from the other supply lines to reduce cross-coupling between power supplies.
LOGIC GND1
7
Ground for the internal logic 1
LOGIC GND2
19
Ground for the internal logic 2
NC
9, 10, 11,
No internal connection
20, 28,
29, 30,
32
PFD INHIBIT1
33
I PFD inhibit 1 control. When PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state (see
Table 4).
PFD INHIBIT2
21
I PFD inhibit 2 control. When PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state (see
Table 5).
PFD OUT1
6
O PFD1 output. When the PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state.
PFD OUT2
SELECT1
SELECT2
18
O PFD2 output. When the PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state.
2
I
 VCO1 output frequency select. When SELECT1 is high, the VCO1 output frequency is 1/2 and when
 SELECT1 is low, the output frequency is 1 (see Table 1).
14
I
 VCO2 output frequency select. When SELECT2 is high, the VCO2 output frequency is 1/2 and when
 SELECT2 is low, the output frequency is 1 (see Table 1).
VCO GND1
35
Ground for VCO1
VCO GND2
23
Ground for VCO2
VCOINHIBIT1
34
I VCO1 inhibit control. When VCOINHIBIT1 is high, VCO OUT1 is low (see Table 2).
VCOINHIBIT2
22
O VCO2 inhibit control. When VCOINHIBIT2 is high, VCO OUT2 is low (see Table 3).
VCO OUT1
3
O VCO1 output. When VCOINHIBIT1 is high, VCO OUT1 is low.
VCO OUT2
15
VCO2 output. When VCOINHIBIT2 is high, VCO OUT2 is low.
VCO VDD1
VCO VDD2
VCOIN1
38
VCO1 supply voltage. VCO VDD1 supplies voltage for VCO1. VCO VDD1 should be separated from LOGIC
VDD1 and LOGIC VDD2 and VCO VDD2 to reduce cross-coupling between power supplies.
26
VCO2 supply voltage. VCO VDD2 supplies voltage for VCO2. VCO VDD2 should be separated from LOGIC
VDD1 and LOGIC VDD2 and VCO VDD1 to reduce cross-coupling between power supplies.
36
I VCO1 control voltage input. Nominally the external loop filter output1 connects to VCOIN1 to control VCO1
oscillation frequency.
VCOIN2
24
I VCO2 control voltage input. Nominally the external loop filter output2 connects to VCOIN2 to control VCO2
oscillation frequency.
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