TL16PNP200A Datasheet, PDF (6/24 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP200A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS274A– APRIL1997 – REVISED MAY 1997
EEPROM interface
This device interfaces to a SGS Thomson 2-Kbit ST93C56, or 4-Kbit ST93C66 compatible EEPROM. In addition
to the three EEPROM signals (SCS, SCLK, and SIO), the two interface signals (PNP_BUSY and SROM_BUSY)
are provided to allow optional on-board logic access to the EEPROM. On power-up or reset, the TL16PNP200A
gains access to the EEPROM and asserts the PNP_BUSY output high indicating that the device is in the
configuration mode and is accessing the EEPROM. After the configuration is complete, the device goes to the
wait-for-key state, puts SIO, SCLK, and SCS outputs into a high impedance state (these signals are pulled down
internally), and deasserts the PNP_BUSY signal. On-board logic can assert to the SROM_BUSY signal at any
time to request access to the EEPROM, then SROM_BUSY can start accessing the EEPROM after two clock
cycles when PNP_BUSY is deasserted; otherwise, SROM_BUSY must wait until PNP_BUSY is deasserted.
In a similar manner, the device uses the PNP_BUSY signal to request access to the EEPROM. In that case
on-board logic will stop accessing the EEPROM and deassert SROM_BUSY, after which the device starts
accessing the EEPROM (see Figure 1). If on-board logic does not need to access the EEPROM, SROM_BUSY
must be tied to ground and PNP_BUSY must be left unconnected. All unused inputs must be tied to the inactive
state, and all unused outputs must be left open.
NOTE:
If the TL16PNP200A enters the configuration mode again and leaves the wait-for-key state, the
wake command generates a read transaction from address 0x0E, which is the beginning of the card
resource data.
CLK
PNP_BUSY
SROM_BUSY
(1)
(2)
(3)
(4)
(5)
(6)
The following steps reflect the EEPROM interface:
(1) The device finishes accessing the EEPROM.
(2) On-board logic requests access to the EEPROM (can be any time).
(3) On-board logic starts accessing the EEPROM since PNP_BUSY is low.
(4) The device requests access to the EEPROM.
(5) On-board logic relinquishes the EEPROM.
(6) The device starts accessing the EEPROM.
Figure 1. EEPROM Interface Signals
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