TL16PNP200A Datasheet, PDF (20/24 Pages) Texas Instruments – STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

TL16PNP200A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS274A– APRIL1997 – REVISED MAY 1997
PRINCIPLES OF OPERATION
Table 9. PnP Logical Device Configuration Registers (continued)
ADDRESS PORT
0×70
REGISTER NAME
ACCESSIBILITY
INTERRUPT REQUEST LEVEL SELECT
Read/write
This register indicates the selected interrupt level. Bits [3-0] select which interrupt level is used. The TL16PNP200A
supports all 11 interrupts available on the ISA bus.
0×71
INTERRUPT REQUEST TYPE SELECT
This register indicates which type of interrupt is used for the selected IRQ.
Bit[1] : Level, 1 = high, 0 = low
Bit[0] : Type,
1 = level, 0 = edge
Read/write
0×74
Note that at the IRQ outputs of the TL16PNP200A, the interrupt type is the same as the type at the INTR inputs, regardless
of the programmed type.
DMA CHANNEL SELECT
Read/write
This register indicates the selected DMA channel. Bits 2-0 select which DMA channel is in use: 000 selects DMA
channel 0, 111 select DMA channel 7. DMA channel 4, the cascade channel indicates no DMA channel is active. The
TL16PNP200A supports three DMA channels to select from in Mode 0 and five in Mode 1. The DMA mapping register,
loaded on power-up, tells the device which DMA channels are connected to it (see the defaults description section).
EEPROM
The TL16PNP200A interfaces to the SGS Thomson EEPROM ST93C56/66 or an equivalent. The EEPROM
provides the PnP resource data and power-up defaults.
memory organization
The EEPROM must be organized as 128/255 words multiplied by 16 bits; therefore, its ORG terminal must be
connected to V_CC or left unconnected. The memory organization for the EEPROM is shown in Table 10.
Table 10. EEPROM Memory Organization
EEPROM
BIT LOCATION
LOCATION _{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
0
13
Power-up Defaults
14
PnP Resource Data
128/255
EEPROM READ (see Figure 9 and 10)
This device only supports read transactions. The READ op code instruction (number10) must be sent into the
EEPROM. The op code is then followed by an 8-bit-long address for the 16-bit word. The READ op code with
accompanying address directs the EEPROM to output serial data on the EEPROM data terminals D and Q,
which is connected to the TL16PNP200A bidirectional serial data bus (SIO). Specifically, when a READ op code
and address are received, the instruction and address are decoded and the addressed EEPROM data is
transferred into an output shift register in the EEPROM. Each read transaction consists of a start bit, 2-bit op
code (number10), 8-bit address, and 16-bit data. The TL16PNP200A does not accommodate the auto-address
next word feature of the EEPROM.
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