TCA9548A_16 Datasheet, PDF (6/36 Pages) Texas Instruments – Low-Voltage 8-Channel I2C Switch with Reset

TCA9548A
SCPS207F – MAY 2012 – REVISED NOVEMBER 2016
www.ti.com
Electrical Characteristics⁽¹⁾ (continued)
V_CC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V_CC
MIN TYP⁽²⁾
R_ON
Switch-on resistance
V_O = 0.4 V, I_O = 15 mA
V_O = 0.4 V, I_O = 10 mA
4.5 V to 5.5 V
3 V to 3.6 V
2.3 V to 2.7 V
1.65 V to 1.95 V
4
10
5
12
7
15
10
25
MAX
20
30
45
70
UNIT
Ω
6.6 I²C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
MIN
STANDARD MODE
f_scl
t_sch
t_scl
t_sp
t_sds
t_sdh
t_icr
t_icf
t_ocf
t_buf
t_sts
t_sth
t_sps
t_vdL(Data)
t_vdH(Data)
I²C clock frequency
I²C clock high time
I²C clock low time
I²C spike time
I²C serial-data setup time
I²C serial-data hold time
I²C input rise time
I²C input fall time
I²C output (SDn) fall time (10-pF to 400-pF bus)
I²C bus free time between stop and start
I²C start or repeated start condition setup
I²C start or repeated start condition hold
I²C stop condition setup
Valid-data time (high to low)⁽²⁾
SCL low to SDA output low valid
Valid-data time (low to high)⁽²⁾
SCL low to SDA output high valid
t_vd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
C_b
I²C bus capacitive load
FAST MODE
f_scl
I²C clock frequency
t_sch
I²C clock high time
t_scl
I²C clock low time
t_sp
I²C spike time
t_sds
I²C serial-data setup time
t_sdh
I²C serial-data hold time
t_icr
I²C input rise time
0
4
4.7
250
0 ⁽¹⁾
4.7
4.7
4
4
0
0.6
1.3
100
0 ⁽¹⁾
20 + 0.1C_b
(3)
t_icf
I²C input fall time
20 + 0.1C_b
(3)
t_ocf
I²C output (SDn) fall time (10-pF to 400-pF bus)
t_buf
I²C bus free time between stop and start
t_sts
I²C start or repeated start condition setup
t_sth
I²C start or repeated start condition hold
t_sps
I²C stop condition setup
20 + 0.1C_b
(3)
1.3
0.6
0.6
0.6
MAX
UNIT
100 kHz
μs
μs
50 ns
ns
μs
1000 ns
300 ns
300 ns
μs
μs
μs
μs
1 μs
0.6 μs
1 μs
400 pF
400 kHz
μs
μs
50 ns
ns
μs
300 ns
300 ns
300 ns
μs
μs
μs
μs
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the V_IH min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
(2) Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 6)
(3) C_b = total bus capacitance of one bus line in pF
6
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