TCA9548A_16 Datasheet, PDF (16/36 Pages) Texas Instruments – Low-Voltage 8-Channel I2C Switch with Reset

TCA9548A
SCPS207F – MAY 2012 – REVISED NOVEMBER 2016
Master controls SDA line
Slave controls SDA line
Write to one register in a device
Device (Slave) Address (7 bits)
Control Register (8 bits)
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S 1 1 1 0 A2 A1 A0 0 A B7 B6 B5 B4 B3 B2 B1 B0 A P
START
R/W=0 ACK
Figure 10. Write to Register
ACK STOP
8.5.3.2 Reads
Reading from a slave is very similar to writing, but the master sends a START condition, followed by the slave
address with the R/W bit set to 1 (signifying a read). The slave acknowledges the read request, and the master
releases the SDA bus but continues supplying the clock to the slave. During this part of the transaction, the
master becomes the master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.
At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for
more data. Once the master has received the number of bytes it is expecting, it sends a NACK, signaling to the
slave to halt communications and release the bus. The master follows this up with a STOP condition.
Figure 11 shows an example of reading a single byte from a slave register.
Master controls SDA line
Slave controls SDA line
Device (Slave) Address (7 bits)
Control Register (8 bits)
S 1 1 1 0 A2 A1 A0 1 A B7 B6 B5 B4 B3 B2 B1 B0 NA P
START
R/W=1 ACK
Figure 11. Read from Control Register
NACK STOP
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