TCA9548A_16 Datasheet, PDF (25/36 Pages) Texas Instruments – Low-Voltage 8-Channel I2C Switch with Reset

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11 Layout
TCA9548A
SCPS207F – MAY 2012 – REVISED NOVEMBER 2016
11.1 Layout Guidelines
For PCB layout of the TCA9548A, common PCB layout practices must be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I²C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are
connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours and
multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,
using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller
capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all V_DPUX voltages and V_CC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, V_DPUM and V_DPU0 – V_DPU7, may all be on the same layer of
the board with split planes to isolate different voltage potentials.
To reduce the total I²C bus capacitance added by PCB parasitics, data lines (SCn and SDn) must be a short as
possible and the widths of the traces must also be minimized (for example, 5-10 mils depending on copper
weight).
11.2 Layout Example
LEGEND
Partial Power Plane
(inner layer)
Copper Pour
(outer layer)
Via to Power Plane
Via to GND Plane
By-pass/de-coupling
capacitors
To I²C Master
V_DPUM
V_DPU0
V_DPU1
V_DPU2
V_DPU3
GND
V_CC
A0 1
PW package
24 VCC
A1 2
23 SDA
RESET 3
22 SCL
SD0 4
21 A2
SC0 5
20 SC7
SD1 6
19 SD7
SC1 7
18 SC6
SD2 8
17 SD6
SC2 9
16 SC5
SD3 10
15 SD5
SC3 11
14 SC4
GND 12
13 SD4
GND
V_DPU7
V_DPU6
V_DPU5
V_DPU4
Figure 20. Layout Schematic
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