MSP430G2230-EP Datasheet, PDF (6/40 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430G2230-EP
SLAS863 – AUGUST 2012
www.ti.com
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0x0FFFF to
0x0FFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0x0FFFE) contains 0x0FFFF (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources
INTERRUPT SOURCE
Power-up
External reset
Watchdog Timer+
Flash key violation
PC out-of-range⁽¹⁾
NMI
Oscillator fault
Flash memory access violation
INTERRUPT FLAG
PORIFG
RSTIFG
WDTIFG
KEYV ⁽²⁾
NMIIFG
OFIFG
ACCVIFG ^{(2) (3)}
SYSTEM
INTERRUPT
Reset
(non)-maskable,
(non)-maskable,
(non)-maskable
Watchdog Timer+
Timer_A2
Timer_A2
WDTIFG
TACCR0 CCIFG⁽⁴⁾
TACCR1 CCIFG, TAIFG⁽²⁾⁽⁴⁾
maskable
maskable
maskable
ADC10 (MSP430G2230 Only)
USI (MSP430G2230 Only)
ADC10IFG ⁽⁴⁾
USIIFG, USISTTIFG⁽²⁾⁽⁴⁾
I/O Port P1(four flags)
P1IFG.2, P1IFG.5, P1IFG.6, and
P1IFG.7^{(2) (4) (5)}
maskable
maskable
maskable
See ⁽⁶⁾
WORD ADDRESS
0xFFFE
0xFFFC
0xFFFA
0xFFF8
0xFFF4
0xFFF2
0xFFF0
0xFFEE
0xFFEC
0xFFEA
0xFFE8
0xFFE6
0xFFE4
0xFFE2
0xFFE0
0xFFDE to 0xFFC0
PRIORITY
31, highest
30
29
28
26
25
24
23
22
21
20
19
18
17
16
15 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4) Interrupt flags are located in the module.
(5) All eight interrupt flags P1IFG.0 to P1IFG.7 are implemented while four are connected to pins.
(6) The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
6
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